[PowerPC] Add support for HTM registers

This patch adds support for Hardware Transactional Memory registers
for the powerpc linux native and core file targets, and for the
pwoerpc linux server stub.

These registers include both the HTM special-purpose registers (TFHAR,
TEXASR and TFIAR) as well as the set of registers that are
checkpointed (saved) when a transaction is initiated, which the
processor restores in the event of a transaction failure.

The set of checkpointed general-purpose registers is returned by the
linux kernel in the same format as the regular general-purpose
registers, defined in struct pt_regs.  However, the architecture
specifies that only some of the registers present in pt_regs are
checkpointed (GPRs 0-31, CR, XER, LR and CTR).  The kernel fills the
slots for MSR and NIP with other info.  The other fields usually don't
have meaningful values.  GDB doesn't define registers that are not
checkpointed in the architecture, but when generating a core file, GDB
fills the slot for the checkpointed MSR with the regular MSR.  These
are usually similar, although some bits might be different, and in
some cases the checkpointed MSR will have a value of 0 in a
kernel-generated core-file.  The checkpointed NIP is filled with TFHAR
by GDB in the core-file, which is what the kernel does.  The other
fields are set to 0 by GDB.

Core files generated by the kernel have a note section for
checkpointed GPRs with the same size for both 32-bit and 64-bit
threads, and the values for the registers of a 32-bit thread are
squeezed in the first half, with no useful data in the second half.
GDB generates a smaller note section for 32-bit threads, but can read
both sizes.

The checkpointed XER is required to be 32-bit in the target
description documentation, even though the more recent ISAs define it
as 64-bit wide, since the high-order 32-bits are reserved, and because
in Linux there is no way to get a 64-bit checkpointed XER for 32-bit
threads.  If this changes in the future, the target description
feature requirement can be relaxed to allow for a 64-bit checkpointed
XER.

Access to the checkpointed CR (condition register) can be confusing.
The architecture only specifies that CR fields 1 to 7 (the 24 least
significant bits) are checkpointed, but the kernel provides all 8
fields (32 bits).  The value of field 0 is not masked by ptrace, so it
will sometimes show the result of some kernel operation, probably
treclaim., which sets this field.

The checkpointed registers are marked not to be saved and restored.
Inferior function calls during an active transaction don't work well,
and it's unclear what should be done in this case.  TEXASR and TFIAR
can be altered asynchronously, during transaction failure recording,
so they are also not saved and restored.  For consistency neither is
TFHAR.

Record and replay also doesn't work well when transactions are
involved.  This patch doesn't address this, so the values of the HTM
SPRs will sometimes be innacurate when the record/relay target is
enabled.  For instance, executing a "tbegin." alters TFHAR and TEXASR,
but these changes are not currently recorded.

Because the checkpointed registers are only available when a
transaction is active (or suspended), ptrace can return ENODATA when
gdb tries to read these registers and the inferior is not in a
transactional state.  The registers are set to the unavailable state
when this happens.  When gbd tries to write to one of these registers,
and it is unavailable, an error is raised.

The "fill" functions for checkpointed register sets in the server stub
are not implemented for the same reason as for the EBB register set,
since ptrace can also return ENODATA for checkpointed regsets.  The
same issues with 'G' packets apply here.

Just like for the EBB registers, tracepoints will not mark the
checkpointed registers as unavailable if the inferior was not in a
transaction, so their content will also show 0 instead of
<unavailable> when inspecting trace data.

The new tests record the values of the regular registers before
stepping the inferior through a "tbegin." instruction to start a
transaction, then the checkpointed registers are checked against the
recorded pre-transactional values.  New values are written to the
checkpointed registers and recorded, the inferior continues until the
transaction aborts (which is usually immediately when it is resumed),
and the regular registers are checked against the recorded values,
because the abort should have reverted the registers to these values.

Like for the EBB registers, target_store_registers will ignore the
checkpointed registers when called with -1 as the regno
argument (store all registers in one go).

gdb/ChangeLog:
2018-10-26  Edjunior Barbosa Machado  <emachado@linux.vnet.ibm.com>
	    Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>

	* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_htm_vsx32l)
	(tdesc_powerpc_isa207_htm_vsx64l): Declare.
	* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TM_SPRREGSET)
	(PPC32_LINUX_SIZEOF_CGPRREGSET, PPC64_LINUX_SIZEOF_CGPRREGSET)
	(PPC_LINUX_SIZEOF_CFPRREGSET, PPC_LINUX_SIZEOF_CVMXREGSET)
	(PPC_LINUX_SIZEOF_CVSXREGSET, PPC_LINUX_SIZEOF_CPPRREGSET)
	(PPC_LINUX_SIZEOF_CDSCRREGSET, PPC_LINUX_SIZEOF_CTARREGSET):
	Define.
	(struct ppc_linux_features) <htm>: New field.
	(ppc_linux_no_features): Add initializer for htm field.
	* arch/ppc-linux-common.c (ppc_linux_match_description): Return
	new tdescs.
	* nat/ppc-linux.h (PPC_FEATURE2_HTM, NT_PPC_TM_CGPR)
	(NT_PPC_TM_CFPR, NT_PPC_TM_CVMX, NT_PPC_TM_CVSX)
	(NT_PPC_TM_SPR, NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR):
	Define if not already defined.
	* features/Makefile (WHICH): Add rs6000/powerpc-isa207-htm-vsx32l
	and rs6000/powerpc-isa207-htm-vsx64l.
	(XMLTOC): Add rs6000/powerpc-isa207-htm-vsx32l.xml and
	rs6000/powerpc-isa207-htm-vsx64l.xml.
	* features/rs6000/power-htm-spr.xml: New file.
	* features/rs6000/power-htm-core.xml: New file.
	* features/rs6000/power64-htm-core.xml: New file.
	* features/rs6000/power-htm-fpu.xml: New file.
	* features/rs6000/power-htm-altivec.xml: New file.
	* features/rs6000/power-htm-vsx.xml: New file.
	* features/rs6000/power-htm-ppr.xml: New file.
	* features/rs6000/power-htm-dscr.xml: New file.
	* features/rs6000/power-htm-tar.xml: New file.
	* features/rs6000/powerpc-isa207-htm-vsx32l.xml: New file.
	* features/rs6000/powerpc-isa207-htm-vsx64l.xml: New file.
	* features/rs6000/powerpc-isa207-htm-vsx32l.c: Generate.
	* features/rs6000/powerpc-isa207-htm-vsx64l.c: Generate.
	* regformats/rs6000/powerpc-isa207-htm-vsx32l.dat: Generate.
	* regformats/rs6000/powerpc-isa207-htm-vsx64l.dat: Generate.
	* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
	fetch_regset with HTM regsets.
	(store_register, store_ppc_registers): Call store_regset with HTM
	regsets.
	(ppc_linux_nat_target::read_description): Set htm field in the
	features struct if needed.
	* ppc-linux-tdep.c: Include
	features/rs6000/powerpc-isa207-htm-vsx32l.c and
	features/rs6000/powerpc-isa207-htm-vsx64l.c.
	(ppc32_regmap_tm_spr, ppc32_regmap_cgpr, ppc64_le_regmap_cgpr)
	(ppc64_be_regmap_cgpr, ppc32_regmap_cfpr, ppc32_le_regmap_cvmx)
	(ppc32_be_regmap_cvmx, ppc32_regmap_cvsx, ppc32_regmap_cppr)
	(ppc32_regmap_cdscr, ppc32_regmap_ctar): New globals.
	(ppc32_linux_tm_sprregset, ppc32_linux_cgprregset)
	(ppc64_be_linux_cgprregset, ppc64_le_linux_cgprregset)
	(ppc32_linux_cfprregset, ppc32_le_linux_cvmxregset)
	(ppc32_be_linux_cvmxregset, ppc32_linux_cvsxregset)
	(ppc32_linux_cpprregset, ppc32_linux_cdscrregset)
	(ppc32_linux_ctarregset): New globals.
	(ppc_linux_cgprregset, ppc_linux_cvmxregset): New functions.
	(ppc_linux_collect_core_cpgrregset): New function.
	(ppc_linux_iterate_over_regset_sections): Call back with the htm
	regsets.
	(ppc_linux_core_read_description): Check if the tm spr section is
	present and set htm in the features struct.
	(_initialize_ppc_linux_tdep): Call
	initialize_tdesc_powerpc_isa207_htm_vsx32l and
	initialize_tdesc_powerpc_isa207_htm_vsx64l.
	* ppc-linux-tdep.h (ppc_linux_cgprregset, ppc_linux_cvmxregset):
	Declare.
	(ppc32_linux_tm_sprregset, ppc32_linux_cfprregset)
	(ppc32_linux_cvsxregset, ppc32_linux_cpprregset)
	(ppc32_linux_cdscrregset, ppc32_linux_ctarregset): Declare.
	* ppc-tdep.h (struct gdbarch_tdep) <have_htm_spr, have_htm_core>:
	New fields.
	<have_htm_fpu, have_htm_altivec, have_htm_vsx>:
	Likewise.
	<ppc_cppr_regnum, ppc_cdscr_regnum, ppc_ctar_regnum>: Likewise.
	<ppc_cdl0_regnum, ppc_cvsr0_regnum, ppc_cefpr0_regnum>: Likewise.
	(enum) <PPC_TFHAR_REGNUM, PPC_TEXASR_REGNUM, PPC_TFIAR_REGNUM>:
	New enum fields.
	<PPC_CR0_REGNUM, PPC_CCR_REGNUM, PPC_CXER_REGNUM>: Likewise.
	<PPC_CLR_REGNUM, PPC_CCTR_REGNUM, PPC_CF0_REGNUM>: Likewise.
	<PPC_CFPSCR_REGNUM, PPC_CVR0_REGNUM, PPC_CVSCR_REGNUM>: Likewise.
	<PPC_CVRSAVE_REGNUM, PPC_CVSR0_UPPER_REGNUM>: Likewise.
	<PPC_CPPR_REGNUM, PPC_CDSCR_REGNUM>: Likewise.
	<PPC_CTAR_REGNUM>: Likewise.
	(PPC_IS_TMSPR_REGNUM, PPC_IS_CKPTGP_REGNUM, PPC_IS_CKPTFP_REGNUM)
	(PPC_IS_CKPTVMX_REGNUM, PPC_IS_CKPTVSX_REGNUM): Define.
	* rs6000-tdep.c (IS_CDFP_PSEUDOREG, IS_CVSX_PSEUDOREG)
	(IS_CEFP_PSEUDOREG): Define.
	(rs6000_register_name): Hide the upper halves of checkpointed VSX
	registers.  Return names for the checkpointed DFP, VSX, and EFP
	pseudo registers.
	(rs6000_pseudo_register_type): Remove initial assert and raise an
	internal error in the else clause instead.  Return types for the
	checkpointed DFP, VSX, and EFP pseudo registers.
	(dfp_pseudo_register_read, dfp_pseudo_register_write): Handle
	checkpointed DFP pseudo registers.
	(vsx_pseudo_register_read, vsx_pseudo_register_write): Handle
	checkpointed VSX pseudo registers.
	(efp_pseudo_register_read, efp_pseudo_register_write): Rename
	from efpr_pseudo_register_read and
	efpr_pseudo_register_write.  Handle checkpointed EFP pseudo
	registers.
	(rs6000_pseudo_register_read, rs6000_pseudo_register_write):
	Handle checkpointed DFP, VSX, and EFP registers.
	(dfp_ax_pseudo_register_collect, vsx_ax_pseudo_register_collect)
	(efp_ax_pseudo_register_collect): New functions.
	(rs6000_ax_pseudo_register_collect): Move DFP, VSX and EFP pseudo
	register logic to new functions.  Handle checkpointed DFP, VSX,
	and EFP pseudo registers.
	(rs6000_gdbarch_init): Look for and validate the htm features.
	Include checkpointed DFP, VSX and EFP pseudo-registers.
	* NEWS: Mention access to PPR, DSCR, TAR, EBB/PMU registers and
	HTM registers.

gdb/gdbserver/ChangeLog:
2018-10-26  Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>

	* configure.srv (ipa_ppc_linux_regobj): Add
	powerpc-isa207-htm-vsx32l-ipa.o and
	powerpc-isa207-htm-vsx64l-ipa.o.
	(powerpc*-*-linux*): Add powerpc-isa207-htm-vsx32l.o and
	powerpc-isa207-htm-vsx64l.o to srv_regobj.  Add
	rs6000/power-htm-spr.xml, rs6000/power-htm-core.xml,
	rs6000/power64-htm-core.xml, rs6000/power-htm-fpu.xml,
	rs6000/power-htm-altivec.xml, rs6000/power-htm-vsx.xml,
	rs6000/power-htm-ppr.xml, rs6000/power-htm-dscr.xml,
	rs6000/power-htm-tar.xml, rs6000/powerpc-isa207-htm-vsx32l.xml,
	and rs6000/powerpc-isa207-htm-vsx64l.xml to srv_xmlfiles.
	* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
	<PPC_TDESC_ISA207_HTM_VSX>: New enum value.
	(init_registers_powerpc_isa207_htm_vsx32l)
	(init_registers_powerpc_isa207_htm_vsx64l): Declare.
	* linux-ppc-low.c (ppc_fill_tm_sprregset, ppc_store_tm_sprregset)
	(ppc_store_tm_cgprregset, ppc_store_tm_cfprregset)
	(ppc_store_tm_cvrregset, ppc_store_tm_cvsxregset)
	(ppc_store_tm_cpprregset, ppc_store_tm_cdscrregset)
	(ppc_store_tm_ctarregset): New functions.
	(ppc_regsets): Add entries for HTM regsets.
	(ppc_arch_setup): Set htm in features struct when needed.  Set
	sizes for the HTM regsets.
	(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_HTM_VSX.
	(initialize_low_arch): Call
	init_registers_powerpc_isa207_htm_vsx32l and
	init_registers_powerpc_isa207_htm_vsx64l.
	* linux-ppc-ipa.c (get_ipa_tdesc): Handle
	PPC_TDESC_ISA207_HTM_VSX.
	(initialize_low_tracepoint): Call
	init_registers_powerpc_isa207_htm_vsx32l and
	init_registers_powerpc_isa207_htm_vsx64l.

gdb/testsuite/ChangeLog:
2018-10-26  Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>

	* gdb.arch/powerpc-htm-regs.c: New file.
	* gdb.arch/powerpc-htm-regs.exp: New file.

gdb/doc/ChangeLog:
2018-10-26  Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>

	* gdb.texinfo (PowerPC Features): Describe new features
	"org.gnu.gdb.power.htm.spr", "org.gnu.gdb.power.htm.core",
	"org.gnu.gdb.power.htm.fpu", "org.gnu.gdb.power.htm.altivec",
	"org.gnu.gdb.power.htm.vsx", "org.gnu.gdb.power.htm.ppr",
	"org.gnu.gdb.power.htm.dscr", "org.gnu.gdb.power.htm.tar".

1 files changed, 217 insertions, 1 deletions

diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
index e32815169d8..12cb56a2b20 100644
--- a/gdb/gdbserver/linux-ppc-low.c
+++ b/gdb/gdbserver/linux-ppc-low.c
@@ -600,6 +600,158 @@ ppc_store_pmuregset (struct regcache *regcache, const void *buf)
   supply_register_by_name (regcache, "mmcr0", &regset[32]);
 }
 
+/* Hardware Transactional Memory special-purpose register regset fill
+   function.  */
+
+static void
+ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
+{
+  int i, base;
+  char *regset = (char *) buf;
+
+  base = find_regno (regcache->tdesc, "tfhar");
+  for (i = 0; i < 3; i++)
+    collect_register (regcache, base + i, &regset[i * 8]);
+}
+
+/* Hardware Transactional Memory special-purpose register regset store
+   function.  */
+
+static void
+ppc_store_tm_sprregset (struct regcache *regcache, const void *buf)
+{
+  int i, base;
+  const char *regset = (const char *) buf;
+
+  base = find_regno (regcache->tdesc, "tfhar");
+  for (i = 0; i < 3; i++)
+    supply_register (regcache, base + i, &regset[i * 8]);
+}
+
+/* For the same reasons as the EBB regset, none of the HTM
+   checkpointed regsets have a fill function.  These registers are
+   only available if the inferior is in a transaction.  */
+
+/* Hardware Transactional Memory checkpointed general-purpose regset
+   store function.  */
+
+static void
+ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf)
+{
+  int i, base, size, endian_offset;
+  const char *regset = (const char *) buf;
+
+  base = find_regno (regcache->tdesc, "cr0");
+  size = register_size (regcache->tdesc, base);
+
+  gdb_assert (size == 4 || size == 8);
+
+  for (i = 0; i < 32; i++)
+    supply_register (regcache, base + i, &regset[i * size]);
+
+  endian_offset = 0;
+
+  if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN))
+    endian_offset = 4;
+
+  supply_register_by_name (regcache, "ccr",
+			   &regset[PT_CCR * size + endian_offset]);
+
+  supply_register_by_name (regcache, "cxer",
+			   &regset[PT_XER * size + endian_offset]);
+
+  supply_register_by_name (regcache, "clr", &regset[PT_LNK * size]);
+  supply_register_by_name (regcache, "cctr", &regset[PT_CTR * size]);
+}
+
+/* Hardware Transactional Memory checkpointed floating-point regset
+   store function.  */
+
+static void
+ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf)
+{
+  int i, base;
+  const char *regset = (const char *) buf;
+
+  base = find_regno (regcache->tdesc, "cf0");
+
+  for (i = 0; i < 32; i++)
+    supply_register (regcache, base + i, &regset[i * 8]);
+
+  supply_register_by_name (regcache, "cfpscr", &regset[32 * 8]);
+}
+
+/* Hardware Transactional Memory checkpointed vector regset store
+   function.  */
+
+static void
+ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf)
+{
+  int i, base;
+  const char *regset = (const char *) buf;
+  int vscr_offset = 0;
+
+  base = find_regno (regcache->tdesc, "cvr0");
+
+  for (i = 0; i < 32; i++)
+    supply_register (regcache, base + i, &regset[i * 16]);
+
+  if (__BYTE_ORDER == __BIG_ENDIAN)
+    vscr_offset = 12;
+
+  supply_register_by_name (regcache, "cvscr",
+			   &regset[32 * 16 + vscr_offset]);
+
+  supply_register_by_name (regcache, "cvrsave", &regset[33 * 16]);
+}
+
+/* Hardware Transactional Memory checkpointed vector-scalar regset
+   store function.  */
+
+static void
+ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf)
+{
+  int i, base;
+  const char *regset = (const char *) buf;
+
+  base = find_regno (regcache->tdesc, "cvs0h");
+  for (i = 0; i < 32; i++)
+    supply_register (regcache, base + i, &regset[i * 8]);
+}
+
+/* Hardware Transactional Memory checkpointed Program Priority
+   Register regset store function.  */
+
+static void
+ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf)
+{
+  const char *cppr = (const char *) buf;
+
+  supply_register_by_name (regcache, "cppr", cppr);
+}
+
+/* Hardware Transactional Memory checkpointed Data Stream Control
+   Register regset store function.  */
+
+static void
+ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf)
+{
+  const char *cdscr = (const char *) buf;
+
+  supply_register_by_name (regcache, "cdscr", cdscr);
+}
+
+/* Hardware Transactional Memory checkpointed Target Address Register
+   regset store function.  */
+
+static void
+ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf)
+{
+  const char *ctar = (const char *) buf;
+
+  supply_register_by_name (regcache, "ctar", ctar);
+}
+
 static void
 ppc_fill_vsxregset (struct regcache *regcache, void *buf)
 {
@@ -709,6 +861,22 @@ static struct regset_info ppc_regsets[] = {
      fetch them every time, but still fall back to PTRACE_PEEKUSER for the
      general registers.  Some kernels support these, but not the newer
      PPC_PTRACE_GETREGS.  */
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS,
+    NULL, ppc_store_tm_ctarregset },
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS,
+    NULL, ppc_store_tm_cdscrregset },
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS,
+    NULL, ppc_store_tm_cpprregset },
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS,
+    NULL, ppc_store_tm_cvsxregset },
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS,
+    NULL, ppc_store_tm_cvrregset },
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS,
+    NULL, ppc_store_tm_cfprregset },
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS,
+    NULL, ppc_store_tm_cgprregset },
+  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
+    ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
   { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
     NULL, ppc_store_ebbregset },
   { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
@@ -800,7 +968,13 @@ ppc_arch_setup (void)
 			       PPC_LINUX_SIZEOF_EBBREGSET)
 	  && ppc_check_regset (tid, NT_PPC_PMU,
 			       PPC_LINUX_SIZEOF_PMUREGSET))
-	features.isa207 = true;
+	{
+	  features.isa207 = true;
+	  if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
+	      && ppc_check_regset (tid, NT_PPC_TM_SPR,
+				   PPC_LINUX_SIZEOF_TM_SPRREGSET))
+	    features.htm = true;
+	}
     }
 
   if (ppc_hwcap & PPC_FEATURE_CELL)
@@ -870,6 +1044,42 @@ ppc_arch_setup (void)
 	    regset->size = (features.isa207 ?
 			    PPC_LINUX_SIZEOF_PMUREGSET : 0);
 	    break;
+	  case NT_PPC_TM_SPR:
+	    regset->size = (features.htm ?
+			    PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
+	    break;
+	  case NT_PPC_TM_CGPR:
+	    if (features.wordsize == 4)
+	      regset->size = (features.htm ?
+			      PPC32_LINUX_SIZEOF_CGPRREGSET : 0);
+	    else
+	      regset->size = (features.htm ?
+			      PPC64_LINUX_SIZEOF_CGPRREGSET : 0);
+	    break;
+	  case NT_PPC_TM_CFPR:
+	    regset->size = (features.htm ?
+			    PPC_LINUX_SIZEOF_CFPRREGSET : 0);
+	    break;
+	  case NT_PPC_TM_CVMX:
+	    regset->size = (features.htm ?
+			    PPC_LINUX_SIZEOF_CVMXREGSET : 0);
+	    break;
+	  case NT_PPC_TM_CVSX:
+	    regset->size = (features.htm ?
+			    PPC_LINUX_SIZEOF_CVSXREGSET : 0);
+	    break;
+	  case NT_PPC_TM_CPPR:
+	    regset->size = (features.htm ?
+			    PPC_LINUX_SIZEOF_CPPRREGSET : 0);
+	    break;
+	  case NT_PPC_TM_CDSCR:
+	    regset->size = (features.htm ?
+			    PPC_LINUX_SIZEOF_CDSCRREGSET : 0);
+	    break;
+	  case NT_PPC_TM_CTAR:
+	    regset->size = (features.htm ?
+			    PPC_LINUX_SIZEOF_CTARREGSET : 0);
+	    break;
 	  default:
 	    break;
 	  }
@@ -3253,6 +3463,8 @@ ppc_get_ipa_tdesc_idx (void)
     return PPC_TDESC_ISA205_PPR_DSCR_VSX;
   if (tdesc == tdesc_powerpc_isa207_vsx64l)
     return PPC_TDESC_ISA207_VSX;
+  if (tdesc == tdesc_powerpc_isa207_htm_vsx64l)
+    return PPC_TDESC_ISA207_HTM_VSX;
 #endif
 
   if (tdesc == tdesc_powerpc_32l)
@@ -3273,6 +3485,8 @@ ppc_get_ipa_tdesc_idx (void)
     return PPC_TDESC_ISA205_PPR_DSCR_VSX;
   if (tdesc == tdesc_powerpc_isa207_vsx32l)
     return PPC_TDESC_ISA207_VSX;
+  if (tdesc == tdesc_powerpc_isa207_htm_vsx32l)
+    return PPC_TDESC_ISA207_HTM_VSX;
   if (tdesc == tdesc_powerpc_e500l)
     return PPC_TDESC_E500;
 
@@ -3333,6 +3547,7 @@ initialize_low_arch (void)
   init_registers_powerpc_isa205_vsx32l ();
   init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
   init_registers_powerpc_isa207_vsx32l ();
+  init_registers_powerpc_isa207_htm_vsx32l ();
   init_registers_powerpc_e500l ();
 #if __powerpc64__
   init_registers_powerpc_64l ();
@@ -3344,6 +3559,7 @@ initialize_low_arch (void)
   init_registers_powerpc_isa205_vsx64l ();
   init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
   init_registers_powerpc_isa207_vsx64l ();
+  init_registers_powerpc_isa207_htm_vsx64l ();
 #endif
 
   initialize_regsets_info (&ppc_regsets_info);