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* Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist2018-04-271-40/+0
* Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist2018-04-261-0/+40
* x86: fold various non-memory operand AVX512VL templatesJan Beulich2018-04-261-17/+54
* x86: also optimize zeroing-masking variants of insnsJan Beulich2018-04-261-1/+1
* x86: properly force / avoid forcing EVEX encodingJan Beulich2018-04-261-7/+5
* x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich2018-04-261-11/+13
* x86: don't recognize bnd<N> as registers without CpuMPXJan Beulich2018-04-261-0/+3
* x86: x87-related adjustmentsJan Beulich2018-04-261-6/+5
* x86: fix indentation in build_modrm_byte()Jan Beulich2018-04-261-39/+39
* x86: move and fold common code in build_modrm_byte()Jan Beulich2018-04-261-29/+13
* x86: drop VexImmExtJan Beulich2018-04-261-7/+3
* x86: tighten assertion in build_modrm_byte()Jan Beulich2018-04-261-4/+3
* x86: drop dead code from build_modrm_byte()Jan Beulich2018-04-261-19/+4
* [ARM] Add TLS relocations for FDPIC.Christophe Lyon2018-04-251-1/+25
* [ARM] Add FDPIC relocations definitionsChristophe Lyon2018-04-251-1/+26
* [ARM] Add FDPIC OSABI flag support.Christophe Lyon2018-04-251-3/+31
* Remove arm-aout and arm-coff supportAlan Modra2018-04-253-73/+2
* Silence gcc-8 warningsAlan Modra2018-04-232-4/+8
* RISC-V: Add new option -mrelax/-mno-relax.Jim Wilson2018-04-201-0/+14
* various i386-aout and i386-coff target removalAlan Modra2018-04-185-187/+0
* [MicroBlaze] PIC data text relativeMichael Eager2018-04-171-9/+36
* Enable Intel CLDEMOTE instruction.Igor Tsimbalist2018-04-171-0/+2
* Fix illegal memory accesses in the assembler when attempting to parse corrup ...Nick Clifton2018-04-161-1/+2
* Remove arm-epoc-pe supportAlan Modra2018-04-162-30/+1
* Remove sparc-aout and sparc-coff supportAlan Modra2018-04-164-264/+6
* Remove m68k-aout and m68k-coff supportAlan Modra2018-04-164-285/+4
* Remove sh5 and sh64 supportAlan Modra2018-04-163-4309/+5
* Remove sh-symbianelf supportAlan Modra2018-04-162-10/+0
* Remove i370 supportAlan Modra2018-04-163-2738/+0
* Remove h8500 supportAlan Modra2018-04-161-5/+0
* Remove h8300-coff supportAlan Modra2018-04-163-54/+5
* Remove netware supportAlan Modra2018-04-162-29/+0
* Enable Intel WAITPKG instructions.Igor Tsimbalist2018-04-111-0/+2
* Remove i860, i960, bout and aout-adobe targetsAlan Modra2018-04-1110-4936/+5
* Make power8 the default cpu when assembling for 64-bit little endian targets.Peter Bergner2018-03-301-1/+5
* [1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li2018-03-281-6/+46
* x86: drop VecESizeJan Beulich2018-03-281-14/+12
* x86: convert broadcast insn attribute to booleanJan Beulich2018-03-281-25/+45
* x86: fold to-scalar-int conversion insnsJan Beulich2018-03-281-2/+6
* Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton2018-03-281-0/+20
* x86: use local variable in check_VecOperands()Jan Beulich2018-03-221-7/+8
* ix86: allow HLE store of accumulator to absolute addressJan Beulich2018-03-221-0/+8
* x86/Intel: fix fallout from earlier template foldingJan Beulich2018-03-221-2/+5
* x86: fold a few XOP templatesJan Beulich2018-03-221-4/+8
* RISC-V: Emit better warning for unknown CSR.Jim Wilson2018-03-161-6/+11
* RISC-V: Add .insn support.Jim Wilson2018-03-141-27/+413
* x86: Encode EVEX instructions with VEX128 if possibleH.J. Lu2018-03-091-1/+2
* x86: Strip whitespace in check_VecOperationsH.J. Lu2018-03-091-0/+6
* x86: Optimize with EVEX128 encoding for AVX512VLH.J. Lu2018-03-081-8/+11
* x86-64: Also optimize "clr reg64"H.J. Lu2018-03-081-7/+12