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path: root/opcodes/i386-dis.c
Commit message (Expand)AuthorAgeFilesLines
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-071-0/+2
* x86: adjust register names printed for MONITOR/MWAITJan Beulich2019-11-071-16/+12
* x86: fold OP_Mwaitx() into OP_Mwait()Jan Beulich2019-11-051-24/+5
* x86: split MONITORX/MWAITX entriesJan Beulich2019-11-051-2/+14
* x86: consolidate disassembler enum naming a littleJan Beulich2019-11-051-75/+75
* x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D}Jan Beulich2019-07-011-13/+4
* x86: drop a few dead macrosJan Beulich2019-07-011-5/+0
* i386: Check vector length for scatter/gather prefetch instructionsH.J. Lu2019-06-271-0/+12
* x86: fold AVX scalar to/from int conversion insnsJan Beulich2019-06-271-48/+6
* x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich2019-06-271-33/+30
* x86: drop dqa_modeJan Beulich2019-06-251-10/+0
* x86: simplify OP_I64()Jan Beulich2019-06-251-40/+3
* x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich2019-06-251-7/+7
* i386: Break i386-dis-evex.h into small filesH.J. Lu2019-06-211-19/+9
* i386: Check vector length for EVEX broadcast instructionsH.J. Lu2019-06-191-0/+10
* i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu2019-06-171-1/+13
* i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu2019-06-051-1/+9
* i386: Check for reserved VEX.vvvv and EVEX.vvvvH.J. Lu2019-06-041-10/+14
* Enable Intel AVX512_VP2INTERSECT insnH.J. Lu2019-06-041-0/+2
* Add support for Intel ENQCMD[S] instructionsH.J. Lu2019-06-041-1/+12
* x86: Support Intel AVX512 BF16Xuepeng Guo2019-04-051-0/+3
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich2018-11-061-2/+0
* x86: correctly handle KMOVD with VEX.W set outside of 64-bit modeJan Beulich2018-11-061-32/+8
* x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich2018-11-061-32/+12
* x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu2018-10-051-1/+1
* x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu2018-09-171-1/+40
* x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu2018-09-171-2/+0
* x86: Update disassembler for VexWIGH.J. Lu2018-09-171-1563/+232
* x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu2018-09-151-2/+0
* x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu2018-09-141-0/+11
* x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu2018-09-141-0/+8
* i386: Reformat OP_E_memoryH.J. Lu2018-09-141-2/+2
* x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich2018-09-131-3/+14
* x86-64: Display eiz for address with the addr32 prefixH.J. Lu2018-08-141-7/+23
* Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu2018-05-071-2/+46
* Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist2018-04-271-50/+4
* Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist2018-04-261-4/+50
* Enable Intel CLDEMOTE instruction.Igor Tsimbalist2018-04-171-1/+28
* x86: Allow 32-bit registers for tpause and umwaitH.J. Lu2018-04-151-2/+2
* Enable Intel WAITPKG instructions.Igor Tsimbalist2018-04-111-4/+31
* i386: Clear vex instead of vex.evexH.J. Lu2018-04-041-6/+1
* x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich2018-03-281-24/+14
* x86: fix swapped operand handling for BNDMOVJan Beulich2018-03-221-3/+11
* x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich2018-03-081-8/+8
* Enable Intel PCONFIG instruction.Igor Tsimbalist2018-01-231-0/+1
* Enable Intel WBNOINVD instruction.Igor Tsimbalist2018-01-231-1/+8
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* x86: don't omit disambiguating suffixes from "fi*"Jan Beulich2017-11-241-12/+12
* x86: fix AVX-512 16-bit addressingJan Beulich2017-11-231-0/+2