diff options
Diffstat (limited to '1009_linux-3.2.10.patch')
| -rw-r--r-- | 1009_linux-3.2.10.patch | 4275 |
1 files changed, 4275 insertions, 0 deletions
diff --git a/1009_linux-3.2.10.patch b/1009_linux-3.2.10.patch new file mode 100644 index 00000000..e5ac4c7d --- /dev/null +++ b/1009_linux-3.2.10.patch @@ -0,0 +1,4275 @@ +diff --git a/Documentation/hwmon/jc42 b/Documentation/hwmon/jc42 +index a22ecf4..52729a7 100644 +--- a/Documentation/hwmon/jc42 ++++ b/Documentation/hwmon/jc42 +@@ -7,21 +7,29 @@ Supported chips: + Addresses scanned: I2C 0x18 - 0x1f + Datasheets: + http://www.analog.com/static/imported-files/data_sheets/ADT7408.pdf +- * IDT TSE2002B3, TS3000B3 +- Prefix: 'tse2002b3', 'ts3000b3' ++ * Atmel AT30TS00 ++ Prefix: 'at30ts00' + Addresses scanned: I2C 0x18 - 0x1f + Datasheets: +- http://www.idt.com/products/getdoc.cfm?docid=18715691 +- http://www.idt.com/products/getdoc.cfm?docid=18715692 ++ http://www.atmel.com/Images/doc8585.pdf ++ * IDT TSE2002B3, TSE2002GB2, TS3000B3, TS3000GB2 ++ Prefix: 'tse2002', 'ts3000' ++ Addresses scanned: I2C 0x18 - 0x1f ++ Datasheets: ++ http://www.idt.com/sites/default/files/documents/IDT_TSE2002B3C_DST_20100512_120303152056.pdf ++ http://www.idt.com/sites/default/files/documents/IDT_TSE2002GB2A1_DST_20111107_120303145914.pdf ++ http://www.idt.com/sites/default/files/documents/IDT_TS3000B3A_DST_20101129_120303152013.pdf ++ http://www.idt.com/sites/default/files/documents/IDT_TS3000GB2A1_DST_20111104_120303151012.pdf + * Maxim MAX6604 + Prefix: 'max6604' + Addresses scanned: I2C 0x18 - 0x1f + Datasheets: + http://datasheets.maxim-ic.com/en/ds/MAX6604.pdf +- * Microchip MCP9805, MCP98242, MCP98243, MCP9843 +- Prefixes: 'mcp9805', 'mcp98242', 'mcp98243', 'mcp9843' ++ * Microchip MCP9804, MCP9805, MCP98242, MCP98243, MCP9843 ++ Prefixes: 'mcp9804', 'mcp9805', 'mcp98242', 'mcp98243', 'mcp9843' + Addresses scanned: I2C 0x18 - 0x1f + Datasheets: ++ http://ww1.microchip.com/downloads/en/DeviceDoc/22203C.pdf + http://ww1.microchip.com/downloads/en/DeviceDoc/21977b.pdf + http://ww1.microchip.com/downloads/en/DeviceDoc/21996a.pdf + http://ww1.microchip.com/downloads/en/DeviceDoc/22153c.pdf +@@ -48,6 +56,12 @@ Supported chips: + Datasheets: + http://www.st.com/stonline/products/literature/ds/13447/stts424.pdf + http://www.st.com/stonline/products/literature/ds/13448/stts424e02.pdf ++ * ST Microelectronics STTS2002, STTS3000 ++ Prefix: 'stts2002', 'stts3000' ++ Addresses scanned: I2C 0x18 - 0x1f ++ Datasheets: ++ http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00225278.pdf ++ http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/CD00270920.pdf + * JEDEC JC 42.4 compliant temperature sensor chips + Prefix: 'jc42' + Addresses scanned: I2C 0x18 - 0x1f +diff --git a/Makefile b/Makefile +index 5f1739b..1ddd6e9 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,6 +1,6 @@ + VERSION = 3 + PATCHLEVEL = 2 +-SUBLEVEL = 9 ++SUBLEVEL = 10 + EXTRAVERSION = + NAME = Saber-toothed Squirrel + +diff --git a/arch/alpha/include/asm/futex.h b/arch/alpha/include/asm/futex.h +index e8a761a..f939794 100644 +--- a/arch/alpha/include/asm/futex.h ++++ b/arch/alpha/include/asm/futex.h +@@ -108,7 +108,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + " lda $31,3b-2b(%0)\n" + " .previous\n" + : "+r"(ret), "=&r"(prev), "=&r"(cmp) +- : "r"(uaddr), "r"((long)oldval), "r"(newval) ++ : "r"(uaddr), "r"((long)(int)oldval), "r"(newval) + : "memory"); + + *uval = prev; +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index b259c7c..ab3740e 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1272,7 +1272,7 @@ config ARM_ERRATA_743622 + depends on CPU_V7 + help + This option enables the workaround for the 743622 Cortex-A9 +- (r2p0..r2p2) erratum. Under very rare conditions, a faulty ++ (r2p*) erratum. Under very rare conditions, a faulty + optimisation in the Cortex-A9 Store Buffer may lead to data + corruption. This workaround sets a specific bit in the diagnostic + register of the Cortex-A9 which disables the Store Buffer +diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h +index 0bda22c..665ef2c 100644 +--- a/arch/arm/include/asm/pmu.h ++++ b/arch/arm/include/asm/pmu.h +@@ -125,7 +125,7 @@ int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type); + + u64 armpmu_event_update(struct perf_event *event, + struct hw_perf_event *hwc, +- int idx, int overflow); ++ int idx); + + int armpmu_event_set_period(struct perf_event *event, + struct hw_perf_event *hwc, +diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c +index 88b0941..ecebb89 100644 +--- a/arch/arm/kernel/perf_event.c ++++ b/arch/arm/kernel/perf_event.c +@@ -187,7 +187,7 @@ armpmu_event_set_period(struct perf_event *event, + u64 + armpmu_event_update(struct perf_event *event, + struct hw_perf_event *hwc, +- int idx, int overflow) ++ int idx) + { + struct arm_pmu *armpmu = to_arm_pmu(event->pmu); + u64 delta, prev_raw_count, new_raw_count; +@@ -200,13 +200,7 @@ again: + new_raw_count) != prev_raw_count) + goto again; + +- new_raw_count &= armpmu->max_period; +- prev_raw_count &= armpmu->max_period; +- +- if (overflow) +- delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; +- else +- delta = new_raw_count - prev_raw_count; ++ delta = (new_raw_count - prev_raw_count) & armpmu->max_period; + + local64_add(delta, &event->count); + local64_sub(delta, &hwc->period_left); +@@ -223,7 +217,7 @@ armpmu_read(struct perf_event *event) + if (hwc->idx < 0) + return; + +- armpmu_event_update(event, hwc, hwc->idx, 0); ++ armpmu_event_update(event, hwc, hwc->idx); + } + + static void +@@ -239,7 +233,7 @@ armpmu_stop(struct perf_event *event, int flags) + if (!(hwc->state & PERF_HES_STOPPED)) { + armpmu->disable(hwc, hwc->idx); + barrier(); /* why? */ +- armpmu_event_update(event, hwc, hwc->idx, 0); ++ armpmu_event_update(event, hwc, hwc->idx); + hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; + } + } +@@ -519,7 +513,13 @@ __hw_perf_event_init(struct perf_event *event) + hwc->config_base |= (unsigned long)mapping; + + if (!hwc->sample_period) { +- hwc->sample_period = armpmu->max_period; ++ /* ++ * For non-sampling runs, limit the sample_period to half ++ * of the counter width. That way, the new counter value ++ * is far less likely to overtake the previous one unless ++ * you have some serious IRQ latency issues. ++ */ ++ hwc->sample_period = armpmu->max_period >> 1; + hwc->last_period = hwc->sample_period; + local64_set(&hwc->period_left, hwc->sample_period); + } +diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c +index e63d811..0ad3c6f 100644 +--- a/arch/arm/kernel/perf_event_v6.c ++++ b/arch/arm/kernel/perf_event_v6.c +@@ -463,23 +463,6 @@ armv6pmu_enable_event(struct hw_perf_event *hwc, + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + } + +-static int counter_is_active(unsigned long pmcr, int idx) +-{ +- unsigned long mask = 0; +- if (idx == ARMV6_CYCLE_COUNTER) +- mask = ARMV6_PMCR_CCOUNT_IEN; +- else if (idx == ARMV6_COUNTER0) +- mask = ARMV6_PMCR_COUNT0_IEN; +- else if (idx == ARMV6_COUNTER1) +- mask = ARMV6_PMCR_COUNT1_IEN; +- +- if (mask) +- return pmcr & mask; +- +- WARN_ONCE(1, "invalid counter number (%d)\n", idx); +- return 0; +-} +- + static irqreturn_t + armv6pmu_handle_irq(int irq_num, + void *dev) +@@ -509,7 +492,8 @@ armv6pmu_handle_irq(int irq_num, + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc; + +- if (!counter_is_active(pmcr, idx)) ++ /* Ignore if we don't have an event. */ ++ if (!event) + continue; + + /* +@@ -520,7 +504,7 @@ armv6pmu_handle_irq(int irq_num, + continue; + + hwc = &event->hw; +- armpmu_event_update(event, hwc, idx, 1); ++ armpmu_event_update(event, hwc, idx); + data.period = event->hw.last_period; + if (!armpmu_event_set_period(event, hwc, idx)) + continue; +diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c +index 1ef6d00..1049319 100644 +--- a/arch/arm/kernel/perf_event_v7.c ++++ b/arch/arm/kernel/perf_event_v7.c +@@ -878,6 +878,11 @@ static inline int armv7_pmnc_disable_intens(int idx) + + counter = ARMV7_IDX_TO_COUNTER(idx); + asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); ++ isb(); ++ /* Clear the overflow flag in case an interrupt is pending. */ ++ asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); ++ isb(); ++ + return idx; + } + +@@ -1024,6 +1029,10 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc; + ++ /* Ignore if we don't have an event. */ ++ if (!event) ++ continue; ++ + /* + * We have a single interrupt for all counters. Check that + * each counter has overflowed before we process it. +@@ -1032,7 +1041,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) + continue; + + hwc = &event->hw; +- armpmu_event_update(event, hwc, idx, 1); ++ armpmu_event_update(event, hwc, idx); + data.period = event->hw.last_period; + if (!armpmu_event_set_period(event, hwc, idx)) + continue; +diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c +index e0cca10..9fc2c95 100644 +--- a/arch/arm/kernel/perf_event_xscale.c ++++ b/arch/arm/kernel/perf_event_xscale.c +@@ -253,11 +253,14 @@ xscale1pmu_handle_irq(int irq_num, void *dev) + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc; + ++ if (!event) ++ continue; ++ + if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) + continue; + + hwc = &event->hw; +- armpmu_event_update(event, hwc, idx, 1); ++ armpmu_event_update(event, hwc, idx); + data.period = event->hw.last_period; + if (!armpmu_event_set_period(event, hwc, idx)) + continue; +@@ -590,11 +593,14 @@ xscale2pmu_handle_irq(int irq_num, void *dev) + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc; + +- if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx)) ++ if (!event) ++ continue; ++ ++ if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx)) + continue; + + hwc = &event->hw; +- armpmu_event_update(event, hwc, idx, 1); ++ armpmu_event_update(event, hwc, idx); + data.period = event->hw.last_period; + if (!armpmu_event_set_period(event, hwc, idx)) + continue; +@@ -661,7 +667,7 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx) + static void + xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) + { +- unsigned long flags, ien, evtsel; ++ unsigned long flags, ien, evtsel, of_flags; + struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + + ien = xscale2pmu_read_int_enable(); +@@ -670,26 +676,31 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) + switch (idx) { + case XSCALE_CYCLE_COUNTER: + ien &= ~XSCALE2_CCOUNT_INT_EN; ++ of_flags = XSCALE2_CCOUNT_OVERFLOW; + break; + case XSCALE_COUNTER0: + ien &= ~XSCALE2_COUNT0_INT_EN; + evtsel &= ~XSCALE2_COUNT0_EVT_MASK; + evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT; ++ of_flags = XSCALE2_COUNT0_OVERFLOW; + break; + case XSCALE_COUNTER1: + ien &= ~XSCALE2_COUNT1_INT_EN; + evtsel &= ~XSCALE2_COUNT1_EVT_MASK; + evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT; ++ of_flags = XSCALE2_COUNT1_OVERFLOW; + break; + case XSCALE_COUNTER2: + ien &= ~XSCALE2_COUNT2_INT_EN; + evtsel &= ~XSCALE2_COUNT2_EVT_MASK; + evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT; ++ of_flags = XSCALE2_COUNT2_OVERFLOW; + break; + case XSCALE_COUNTER3: + ien &= ~XSCALE2_COUNT3_INT_EN; + evtsel &= ~XSCALE2_COUNT3_EVT_MASK; + evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT; ++ of_flags = XSCALE2_COUNT3_OVERFLOW; + break; + default: + WARN_ONCE(1, "invalid counter number (%d)\n", idx); +@@ -699,6 +710,7 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) + raw_spin_lock_irqsave(&events->pmu_lock, flags); + xscale2pmu_write_event_select(evtsel); + xscale2pmu_write_int_enable(ien); ++ xscale2pmu_write_overflow_flags(of_flags); + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + } + +diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c +index a9e0dae..1620b15 100644 +--- a/arch/arm/mach-dove/common.c ++++ b/arch/arm/mach-dove/common.c +@@ -29,6 +29,7 @@ + #include <asm/mach/arch.h> + #include <linux/irq.h> + #include <plat/time.h> ++#include <plat/ehci-orion.h> + #include <plat/common.h> + #include "common.h" + +@@ -72,7 +73,7 @@ void __init dove_map_io(void) + void __init dove_ehci0_init(void) + { + orion_ehci_init(&dove_mbus_dram_info, +- DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); ++ DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); + } + + /***************************************************************************** +diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c +index f3248cf..c5dbbb3 100644 +--- a/arch/arm/mach-kirkwood/common.c ++++ b/arch/arm/mach-kirkwood/common.c +@@ -28,6 +28,7 @@ + #include <plat/cache-feroceon-l2.h> + #include <plat/mvsdio.h> + #include <plat/orion_nand.h> ++#include <plat/ehci-orion.h> + #include <plat/common.h> + #include <plat/time.h> + #include "common.h" +@@ -74,7 +75,7 @@ void __init kirkwood_ehci_init(void) + { + kirkwood_clk_ctrl |= CGC_USB0; + orion_ehci_init(&kirkwood_mbus_dram_info, +- USB_PHYS_BASE, IRQ_KIRKWOOD_USB); ++ USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); + } + + +diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h +index ac78795..7afccf4 100644 +--- a/arch/arm/mach-kirkwood/mpp.h ++++ b/arch/arm/mach-kirkwood/mpp.h +@@ -31,313 +31,313 @@ + #define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) ++#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) ++#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) ++#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) ++#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +-#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +-#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) ++#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 ) + + #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) +-#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) ++#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 ) ++#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +-#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) ++#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 ) + + #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) +-#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) +-#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) ++#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 ) ++#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 ) ++#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) +-#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +-#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) +-#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) ++#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 ) ++#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 ) ++#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +-#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +-#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +-#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) +-#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) ++#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 ) ++#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 ) ++#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +-#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) ++#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 ) + + #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +-#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +-#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) +-#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) +-#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) +-#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) ++#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 ) ++#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 ) ++#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 ) ++#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 ) + + #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +-#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) +-#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) ++#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 ) ++#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 ) ++#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +-#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) ++#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 ) ++#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +-#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +-#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) +-#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) +-#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) ++#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 ) ++#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 ) ++#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) +-#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) ++#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 ) ++#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +-#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +-#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +-#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) +-#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) ++#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 ) ++#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) +-#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +-#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) ++#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 ) ++#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 ) ++#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) ++#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 ) ++#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +-#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) ++#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +-#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +-#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) ++#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +-#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) ++#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +-#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) ++#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) ++#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) ++#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) ++#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) ++#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) ++#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) ++#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) ++#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +-#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) ++#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 ) ++#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) +-#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +-#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) ++#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 ) + #define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +-#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) ++#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 ) + #define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +-#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) ++#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 ) + #define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +-#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) ++#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 ) + + #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +-#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +-#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) ++#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 ) ++#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +-#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +-#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) ++#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 ) ++#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +-#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) ++#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 ) + #define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +-#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) ++#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 ) + #define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +-#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) ++#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 ) + #define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) +-#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) ++#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 ) + #define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +-#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) ++#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 ) + #define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) ++#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 ) + #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +-#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) ++#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 ) + #define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +-#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) ++#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 ) + #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +-#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) ++#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 ) + #define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) ++#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 ) + #define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) ++#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 ) + #define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) ++#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 ) + #define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +-#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) ++#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 ) + #define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) + #define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) +-#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) +-#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +-#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) +-#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) ++#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 ) ++#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 ) ++#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 ) ++#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 ) + #define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + + #define MPP_MAX 49 +diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h +index 2667f52..9e3b90d 100644 +--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h ++++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h +@@ -61,7 +61,7 @@ + */ + #define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) + #define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) +-#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4) ++#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4) + #define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) + #define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) + #define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) +diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c +index 4eae566..c74de01 100644 +--- a/arch/arm/mach-lpc32xx/irq.c ++++ b/arch/arm/mach-lpc32xx/irq.c +@@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, + }, ++ [IRQ_LPC32XX_GPI_28] = { ++ .event_group = &lpc32xx_event_pin_regs, ++ .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT, ++ }, + [IRQ_LPC32XX_GPIO_00] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, +@@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state) + + if (state) + eventreg |= lpc32xx_events[d->irq].mask; +- else ++ else { + eventreg &= ~lpc32xx_events[d->irq].mask; + ++ /* ++ * When disabling the wakeup, clear the latched ++ * event ++ */ ++ __raw_writel(lpc32xx_events[d->irq].mask, ++ lpc32xx_events[d->irq]. ++ event_group->rawstat_reg); ++ } ++ + __raw_writel(eventreg, + lpc32xx_events[d->irq].event_group->enab_reg); + +@@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void) + + /* Setup SIC1 */ + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); +- __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); +- __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); ++ __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); ++ __raw_writel(SIC1_ATR_DEFAULT, ++ LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); + + /* Setup SIC2 */ + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); +- __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); +- __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); ++ __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); ++ __raw_writel(SIC2_ATR_DEFAULT, ++ LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); + + /* Configure supported IRQ's */ + for (i = 0; i < NR_IRQS; i++) { +diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c +index 429cfdb..f273528 100644 +--- a/arch/arm/mach-lpc32xx/serial.c ++++ b/arch/arm/mach-lpc32xx/serial.c +@@ -88,6 +88,7 @@ struct uartinit { + char *uart_ck_name; + u32 ck_mode_mask; + void __iomem *pdiv_clk_reg; ++ resource_size_t mapbase; + }; + + static struct uartinit uartinit_data[] __initdata = { +@@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = { + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, ++ .mapbase = LPC32XX_UART5_BASE, + }, + #endif + #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT +@@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = { + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, ++ .mapbase = LPC32XX_UART3_BASE, + }, + #endif + #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT +@@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = { + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, ++ .mapbase = LPC32XX_UART4_BASE, + }, + #endif + #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT +@@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = { + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, ++ .mapbase = LPC32XX_UART6_BASE, + }, + #endif + }; +@@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void) + + /* pre-UART clock divider set to 1 */ + __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); ++ ++ /* ++ * Force a flush of the RX FIFOs to work around a ++ * HW bug ++ */ ++ puart = uartinit_data[i].mapbase; ++ __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); ++ __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); ++ j = LPC32XX_SUART_FIFO_SIZE; ++ while (j--) ++ tmp = __raw_readl( ++ LPC32XX_UART_DLL_FIFO(puart)); ++ __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); + } + + /* This needs to be done after all UART clocks are setup */ + __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); +- for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) { ++ for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { + /* Force a flush of the RX FIFOs to work around a HW bug */ + puart = serial_std_platform_data[i].mapbase; + __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); +diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c +index 23d3980..d90e244 100644 +--- a/arch/arm/mach-mv78xx0/common.c ++++ b/arch/arm/mach-mv78xx0/common.c +@@ -20,6 +20,7 @@ + #include <mach/mv78xx0.h> + #include <mach/bridge-regs.h> + #include <plat/cache-feroceon-l2.h> ++#include <plat/ehci-orion.h> + #include <plat/orion_nand.h> + #include <plat/time.h> + #include <plat/common.h> +@@ -170,7 +171,7 @@ void __init mv78xx0_map_io(void) + void __init mv78xx0_ehci0_init(void) + { + orion_ehci_init(&mv78xx0_mbus_dram_info, +- USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); ++ USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); + } + + +diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h +index b61b509..3752302 100644 +--- a/arch/arm/mach-mv78xx0/mpp.h ++++ b/arch/arm/mach-mv78xx0/mpp.h +@@ -24,296 +24,296 @@ + #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) + + #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) +-#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) +-#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) ++#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1) ++#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1) + #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) + + #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) +-#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) +-#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) ++#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1) ++#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1) + #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) + + #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) +-#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) +-#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) ++#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1) ++#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1) + #define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) + + #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) +-#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) +-#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) ++#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1) ++#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1) + #define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) + + #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) +-#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) +-#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) ++#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1) ++#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1) + #define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) + + #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) +-#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) +-#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) ++#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1) ++#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1) + #define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) + + #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) +-#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) +-#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) ++#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1) ++#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1) + #define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) + + #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) +-#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) +-#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) ++#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1) ++#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1) + #define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) + + #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) +-#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) +-#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) ++#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1) ++#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1) + #define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) + + #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) +-#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) +-#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) ++#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1) ++#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1) + #define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) + + #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) +-#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) +-#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) ++#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1) ++#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1) + #define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) + + #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) +-#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) +-#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) ++#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1) ++#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1) + #define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) + + #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) +-#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) +-#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) +-#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) +-#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) ++#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1) ++#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1) ++#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1) ++#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1) + #define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) + + #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) +-#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) +-#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) +-#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) +-#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) ++#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1) ++#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1) ++#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1) ++#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1) + #define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) + + #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) +-#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) +-#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) +-#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) +-#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) ++#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1) ++#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1) ++#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1) ++#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1) + #define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) + + #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) +-#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) +-#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) +-#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) +-#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) ++#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1) ++#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1) ++#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1) ++#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1) + #define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) + + #define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) +-#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) +-#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) +-#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) +-#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) ++#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1) ++#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1) ++#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1) ++#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1) + #define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) + + + #define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) +-#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) +-#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) +-#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) +-#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) ++#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1) ++#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1) ++#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1) ++#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1) + #define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) + + + #define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) +-#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) +-#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) ++#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1) ++#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1) + #define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) + + + + #define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) +-#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) +-#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) ++#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1) ++#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1) + #define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) + + + #define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) +-#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) +-#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) ++#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1) ++#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0) + #define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) + + + + #define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) +-#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) +-#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) ++#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1) ++#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0) + #define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) + + + + #define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) +-#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) +-#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) +-#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) ++#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1) ++#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1) ++#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1) + #define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) + + + + #define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) +-#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) +-#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) +-#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) ++#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1) ++#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1) ++#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1) + #define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) + + + #define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) +-#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) +-#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) ++#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1) ++#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1) + #define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) + + + #define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) +-#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) +-#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) ++#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1) ++#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1) + #define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) + + + #define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) +-#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) +-#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) ++#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1) ++#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1) + #define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) + + + #define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) +-#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) +-#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) ++#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1) ++#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1) + #define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) + + + #define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) +-#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) +-#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) ++#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1) ++#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1) + #define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) + + #define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) +-#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) +-#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) +-#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) ++#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1) ++#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1) ++#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1) + #define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) + + #define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) +-#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) ++#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1) + #define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) + + #define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) +-#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) +-#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) ++#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1) ++#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1) + #define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) + + + #define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) +-#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) +-#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) +-#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) ++#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1) ++#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1) ++#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1) + #define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) + + + #define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) +-#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) +-#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) ++#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1) ++#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1) + #define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) + + + + #define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) +-#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) +-#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) ++#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1) ++#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1) + #define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) + + + + #define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) +-#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) +-#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) ++#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1) ++#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1) + #define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) + + #define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) +-#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) +-#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) +-#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) ++#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1) ++#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1) ++#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1) + #define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) + + + #define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) +-#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) +-#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) +-#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) +-#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) ++#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1) ++#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1) ++#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1) ++#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1) + #define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) + + + + + #define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) +-#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) +-#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) +-#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) +-#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) ++#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1) ++#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1) ++#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1) ++#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1) + #define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) + + + + + #define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) +-#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) +-#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) +-#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) +-#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) ++#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1) ++#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1) ++#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1) ++#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1) + #define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) + + + + #define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) +-#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) ++#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1) + #define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) + + + + #define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) +-#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) ++#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1) + #define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) + + + + #define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) +-#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) ++#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1) + #define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) + + + + #define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) +-#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) ++#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1) + #define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) + + + + #define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) +-#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) ++#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1) + #define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) + + + + #define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) +-#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) +-#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) ++#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1) ++#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1) + #define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) + + + #define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) +-#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) ++#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1) + #define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) + + +@@ -323,14 +323,14 @@ + + + #define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) +-#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) ++#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1) + #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) + + + + #define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) +-#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) +-#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) ++#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1) ++#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1) + #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) + + +diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c +index 5156468..02cd29a 100644 +--- a/arch/arm/mach-omap2/board-4430sdp.c ++++ b/arch/arm/mach-omap2/board-4430sdp.c +@@ -52,8 +52,9 @@ + #define ETH_KS8851_QUART 138 + #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 + #define OMAP4_SFH7741_ENABLE_GPIO 188 +-#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ ++#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */ + #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ ++#define HDMI_GPIO_HPD 63 /* Hotplug detect */ + #define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */ + #define DLP_POWER_ON_GPIO 40 + +@@ -597,12 +598,8 @@ static void __init omap_sfh7741prox_init(void) + + static void sdp4430_hdmi_mux_init(void) + { +- /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ +- omap_mux_init_signal("hdmi_hpd", +- OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_cec", + OMAP_PIN_INPUT_PULLUP); +- /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ + omap_mux_init_signal("hdmi_ddc_scl", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_ddc_sda", +@@ -610,8 +607,9 @@ static void sdp4430_hdmi_mux_init(void) + } + + static struct gpio sdp4430_hdmi_gpios[] = { +- { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, ++ { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, + { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, ++ { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, + }; + + static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) +@@ -628,8 +626,7 @@ static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) + + static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) + { +- gpio_free(HDMI_GPIO_LS_OE); +- gpio_free(HDMI_GPIO_HPD); ++ gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios)); + } + + static struct nokia_dsi_panel_data dsi1_panel = { +@@ -745,6 +742,10 @@ static void sdp4430_lcd_init(void) + pr_err("%s: Could not get lcd2_reset_gpio\n", __func__); + } + ++static struct omap_dss_hdmi_data sdp4430_hdmi_data = { ++ .hpd_gpio = HDMI_GPIO_HPD, ++}; ++ + static struct omap_dss_device sdp4430_hdmi_device = { + .name = "hdmi", + .driver_name = "hdmi_panel", +@@ -752,6 +753,7 @@ static struct omap_dss_device sdp4430_hdmi_device = { + .platform_enable = sdp4430_panel_enable_hdmi, + .platform_disable = sdp4430_panel_disable_hdmi, + .channel = OMAP_DSS_CHANNEL_DIGIT, ++ .data = &sdp4430_hdmi_data, + }; + + static struct picodlp_panel_data sdp4430_picodlp_pdata = { +@@ -829,6 +831,10 @@ static void omap_4430sdp_display_init(void) + sdp4430_hdmi_mux_init(); + sdp4430_picodlp_init(); + omap_display_init(&sdp4430_dss_data); ++ ++ omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); ++ omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); ++ omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); + } + + #ifdef CONFIG_OMAP_MUX +diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c +index a8c2c42..51b1c93 100644 +--- a/arch/arm/mach-omap2/board-omap4panda.c ++++ b/arch/arm/mach-omap2/board-omap4panda.c +@@ -51,8 +51,9 @@ + #define GPIO_HUB_NRESET 62 + #define GPIO_WIFI_PMENA 43 + #define GPIO_WIFI_IRQ 53 +-#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ ++#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */ + #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ ++#define HDMI_GPIO_HPD 63 /* Hotplug detect */ + + /* wl127x BT, FM, GPS connectivity chip */ + static int wl1271_gpios[] = {46, -1, -1}; +@@ -481,12 +482,8 @@ int __init omap4_panda_dvi_init(void) + + static void omap4_panda_hdmi_mux_init(void) + { +- /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ +- omap_mux_init_signal("hdmi_hpd", +- OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_cec", + OMAP_PIN_INPUT_PULLUP); +- /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ + omap_mux_init_signal("hdmi_ddc_scl", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_ddc_sda", +@@ -494,8 +491,9 @@ static void omap4_panda_hdmi_mux_init(void) + } + + static struct gpio panda_hdmi_gpios[] = { +- { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, ++ { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, + { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, ++ { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, + }; + + static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) +@@ -512,10 +510,13 @@ static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) + + static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) + { +- gpio_free(HDMI_GPIO_LS_OE); +- gpio_free(HDMI_GPIO_HPD); ++ gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios)); + } + ++static struct omap_dss_hdmi_data omap4_panda_hdmi_data = { ++ .hpd_gpio = HDMI_GPIO_HPD, ++}; ++ + static struct omap_dss_device omap4_panda_hdmi_device = { + .name = "hdmi", + .driver_name = "hdmi_panel", +@@ -523,6 +524,7 @@ static struct omap_dss_device omap4_panda_hdmi_device = { + .platform_enable = omap4_panda_panel_enable_hdmi, + .platform_disable = omap4_panda_panel_disable_hdmi, + .channel = OMAP_DSS_CHANNEL_DIGIT, ++ .data = &omap4_panda_hdmi_data, + }; + + static struct omap_dss_device *omap4_panda_dss_devices[] = { +@@ -546,6 +548,10 @@ void omap4_panda_display_init(void) + + omap4_panda_hdmi_mux_init(); + omap_display_init(&omap4_panda_dss_data); ++ ++ omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); ++ omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); ++ omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); + } + + static void __init omap4_panda_init(void) +diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c +index b882204..ac49384 100644 +--- a/arch/arm/mach-omap2/omap-iommu.c ++++ b/arch/arm/mach-omap2/omap-iommu.c +@@ -150,7 +150,8 @@ err_out: + platform_device_put(omap_iommu_pdev[i]); + return err; + } +-module_init(omap_iommu_init); ++/* must be ready before omap3isp is probed */ ++subsys_initcall(omap_iommu_init); + + static void __exit omap_iommu_exit(void) + { +diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c +index 22ace0b..53b68b8 100644 +--- a/arch/arm/mach-orion5x/common.c ++++ b/arch/arm/mach-orion5x/common.c +@@ -29,6 +29,7 @@ + #include <mach/hardware.h> + #include <mach/orion5x.h> + #include <plat/orion_nand.h> ++#include <plat/ehci-orion.h> + #include <plat/time.h> + #include <plat/common.h> + #include "common.h" +@@ -72,7 +73,8 @@ void __init orion5x_map_io(void) + void __init orion5x_ehci0_init(void) + { + orion_ehci_init(&orion5x_mbus_dram_info, +- ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); ++ ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, ++ EHCI_PHY_ORION); + } + + +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +index 40cc7aa..82ef81d 100644 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -352,9 +352,7 @@ __v7_setup: + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register + #endif + #ifdef CONFIG_ARM_ERRATA_743622 +- teq r6, #0x20 @ present in r2p0 +- teqne r6, #0x21 @ present in r2p1 +- teqne r6, #0x22 @ present in r2p2 ++ teq r5, #0x00200000 @ only present in r2p* + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register + orreq r10, r10, #1 << 6 @ set bit #6 + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register +diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c +index 9e5451b..11dce87 100644 +--- a/arch/arm/plat-orion/common.c ++++ b/arch/arm/plat-orion/common.c +@@ -806,10 +806,7 @@ void __init orion_xor1_init(unsigned long mapbase_low, + /***************************************************************************** + * EHCI + ****************************************************************************/ +-static struct orion_ehci_data orion_ehci_data = { +- .phy_version = EHCI_PHY_NA, +-}; +- ++static struct orion_ehci_data orion_ehci_data; + static u64 ehci_dmamask = DMA_BIT_MASK(32); + + +@@ -830,9 +827,11 @@ static struct platform_device orion_ehci = { + + void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, +- unsigned long irq) ++ unsigned long irq, ++ enum orion_ehci_phy_ver phy_version) + { + orion_ehci_data.dram = mbus_dram_info; ++ orion_ehci_data.phy_version = phy_version; + fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, + irq); + +diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h +index a63c357..a2c0e31 100644 +--- a/arch/arm/plat-orion/include/plat/common.h ++++ b/arch/arm/plat-orion/include/plat/common.h +@@ -95,7 +95,8 @@ void __init orion_xor1_init(unsigned long mapbase_low, + + void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, +- unsigned long irq); ++ unsigned long irq, ++ enum orion_ehci_phy_ver phy_version); + + void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, +diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c +index 9155343..3b1e17b 100644 +--- a/arch/arm/plat-orion/mpp.c ++++ b/arch/arm/plat-orion/mpp.c +@@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, + gpio_mode |= GPIO_INPUT_OK; + if (*mpp_list & MPP_OUTPUT_MASK) + gpio_mode |= GPIO_OUTPUT_OK; +- if (sel != 0) +- gpio_mode = 0; ++ + orion_gpio_set_valid(num, gpio_mode); + } + +diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c +index 53754bc..8a90b6a 100644 +--- a/arch/arm/plat-s3c24xx/dma.c ++++ b/arch/arm/plat-s3c24xx/dma.c +@@ -1249,7 +1249,7 @@ static void s3c2410_dma_resume(void) + struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1; + int channel; + +- for (channel = dma_channels - 1; channel >= 0; cp++, channel--) ++ for (channel = dma_channels - 1; channel >= 0; cp--, channel--) + s3c2410_dma_resume_chan(cp); + } + +diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig +index 197e96f..3dea7231 100644 +--- a/arch/avr32/Kconfig ++++ b/arch/avr32/Kconfig +@@ -8,6 +8,7 @@ config AVR32 + select HAVE_KPROBES + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE ++ select GENERIC_ATOMIC64 + select HARDIRQS_SW_RESEND + select GENERIC_IRQ_SHOW + select ARCH_HAVE_NMI_SAFE_CMPXCHG +diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig +index 373679b..f929db9 100644 +--- a/arch/s390/Kconfig ++++ b/arch/s390/Kconfig +@@ -230,6 +230,9 @@ config COMPAT + config SYSVIPC_COMPAT + def_bool y if COMPAT && SYSVIPC + ++config KEYS_COMPAT ++ def_bool y if COMPAT && KEYS ++ + config AUDIT_ARCH + def_bool y + +diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h +index 2e49748..234f1d8 100644 +--- a/arch/s390/include/asm/compat.h ++++ b/arch/s390/include/asm/compat.h +@@ -172,13 +172,6 @@ static inline int is_compat_task(void) + return is_32bit_task(); + } + +-#else +- +-static inline int is_compat_task(void) +-{ +- return 0; +-} +- + #endif + + static inline void __user *arch_compat_alloc_user_space(long len) +diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c +index 9451b21..53088e2 100644 +--- a/arch/s390/kernel/process.c ++++ b/arch/s390/kernel/process.c +@@ -29,7 +29,6 @@ + #include <asm/irq.h> + #include <asm/timer.h> + #include <asm/nmi.h> +-#include <asm/compat.h> + #include <asm/smp.h> + #include "entry.h" + +diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c +index 573bc29..afe82bc 100644 +--- a/arch/s390/kernel/ptrace.c ++++ b/arch/s390/kernel/ptrace.c +@@ -20,8 +20,8 @@ + #include <linux/regset.h> + #include <linux/tracehook.h> + #include <linux/seccomp.h> ++#include <linux/compat.h> + #include <trace/syscall.h> +-#include <asm/compat.h> + #include <asm/segment.h> + #include <asm/page.h> + #include <asm/pgtable.h> +diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c +index e54c4ff..773f55e 100644 +--- a/arch/s390/kernel/setup.c ++++ b/arch/s390/kernel/setup.c +@@ -45,6 +45,7 @@ + #include <linux/kexec.h> + #include <linux/crash_dump.h> + #include <linux/memory.h> ++#include <linux/compat.h> + + #include <asm/ipl.h> + #include <asm/uaccess.h> +@@ -58,7 +59,6 @@ + #include <asm/ptrace.h> + #include <asm/sections.h> + #include <asm/ebcdic.h> +-#include <asm/compat.h> + #include <asm/kvm_virtio.h> + #include <asm/diag.h> + +diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c +index 7f6f9f3..5086553 100644 +--- a/arch/s390/kernel/signal.c ++++ b/arch/s390/kernel/signal.c +@@ -30,7 +30,6 @@ + #include <asm/ucontext.h> + #include <asm/uaccess.h> + #include <asm/lowcore.h> +-#include <asm/compat.h> + #include "entry.h" + + #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) +diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c +index a9a3018..c7f0fbc 100644 +--- a/arch/s390/mm/fault.c ++++ b/arch/s390/mm/fault.c +@@ -36,7 +36,6 @@ + #include <asm/pgtable.h> + #include <asm/irq.h> + #include <asm/mmu_context.h> +-#include <asm/compat.h> + #include "../kernel/entry.h" + + #ifndef CONFIG_64BIT +diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c +index f09c748..a0155c0 100644 +--- a/arch/s390/mm/mmap.c ++++ b/arch/s390/mm/mmap.c +@@ -29,8 +29,8 @@ + #include <linux/mman.h> + #include <linux/module.h> + #include <linux/random.h> ++#include <linux/compat.h> + #include <asm/pgalloc.h> +-#include <asm/compat.h> + + static unsigned long stack_maxrandom_size(void) + { +diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h +index f61c62f..50d7ff2 100644 +--- a/arch/x86/include/asm/perf_event.h ++++ b/arch/x86/include/asm/perf_event.h +@@ -212,4 +212,12 @@ static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr) + static inline void perf_events_lapic_init(void) { } + #endif + ++#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) ++ extern void amd_pmu_enable_virt(void); ++ extern void amd_pmu_disable_virt(void); ++#else ++ static inline void amd_pmu_enable_virt(void) { } ++ static inline void amd_pmu_disable_virt(void) { } ++#endif ++ + #endif /* _ASM_X86_PERF_EVENT_H */ +diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h +index b9698d4..02e0295 100644 +--- a/arch/x86/kernel/cpu/perf_event.h ++++ b/arch/x86/kernel/cpu/perf_event.h +@@ -146,7 +146,9 @@ struct cpu_hw_events { + /* + * AMD specific bits + */ +- struct amd_nb *amd_nb; ++ struct amd_nb *amd_nb; ++ /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ ++ u64 perf_ctr_virt_mask; + + void *kfree_on_online; + }; +@@ -372,9 +374,11 @@ void x86_pmu_disable_all(void); + static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, + u64 enable_mask) + { ++ u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); ++ + if (hwc->extra_reg.reg) + wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); +- wrmsrl(hwc->config_base, hwc->config | enable_mask); ++ wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); + } + + void x86_pmu_enable_all(int added); +diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c +index aeefd45..f64a039 100644 +--- a/arch/x86/kernel/cpu/perf_event_amd.c ++++ b/arch/x86/kernel/cpu/perf_event_amd.c +@@ -1,4 +1,5 @@ + #include <linux/perf_event.h> ++#include <linux/export.h> + #include <linux/types.h> + #include <linux/init.h> + #include <linux/slab.h> +@@ -357,7 +358,9 @@ static void amd_pmu_cpu_starting(int cpu) + struct amd_nb *nb; + int i, nb_id; + +- if (boot_cpu_data.x86_max_cores < 2) ++ cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY; ++ ++ if (boot_cpu_data.x86_max_cores < 2 || boot_cpu_data.x86 == 0x15) + return; + + nb_id = amd_get_nb_id(cpu); +@@ -587,9 +590,9 @@ static __initconst const struct x86_pmu amd_pmu_f15h = { + .put_event_constraints = amd_put_event_constraints, + + .cpu_prepare = amd_pmu_cpu_prepare, +- .cpu_starting = amd_pmu_cpu_starting, + .cpu_dead = amd_pmu_cpu_dead, + #endif ++ .cpu_starting = amd_pmu_cpu_starting, + }; + + __init int amd_pmu_init(void) +@@ -621,3 +624,33 @@ __init int amd_pmu_init(void) + + return 0; + } ++ ++void amd_pmu_enable_virt(void) ++{ ++ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); ++ ++ cpuc->perf_ctr_virt_mask = 0; ++ ++ /* Reload all events */ ++ x86_pmu_disable_all(); ++ x86_pmu_enable_all(0); ++} ++EXPORT_SYMBOL_GPL(amd_pmu_enable_virt); ++ ++void amd_pmu_disable_virt(void) ++{ ++ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); ++ ++ /* ++ * We only mask out the Host-only bit so that host-only counting works ++ * when SVM is disabled. If someone sets up a guest-only counter when ++ * SVM is disabled the Guest-only bits still gets set and the counter ++ * will not count anything. ++ */ ++ cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY; ++ ++ /* Reload all events */ ++ x86_pmu_disable_all(); ++ x86_pmu_enable_all(0); ++} ++EXPORT_SYMBOL_GPL(amd_pmu_disable_virt); +diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c +index e32243e..94a4672 100644 +--- a/arch/x86/kvm/svm.c ++++ b/arch/x86/kvm/svm.c +@@ -29,6 +29,7 @@ + #include <linux/ftrace_event.h> + #include <linux/slab.h> + ++#include <asm/perf_event.h> + #include <asm/tlbflush.h> + #include <asm/desc.h> + #include <asm/kvm_para.h> +@@ -575,6 +576,8 @@ static void svm_hardware_disable(void *garbage) + wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); + + cpu_svm_disable(); ++ ++ amd_pmu_disable_virt(); + } + + static int svm_hardware_enable(void *garbage) +@@ -622,6 +625,8 @@ static int svm_hardware_enable(void *garbage) + + svm_init_erratum_383(); + ++ amd_pmu_enable_virt(); ++ + return 0; + } + +diff --git a/block/bsg.c b/block/bsg.c +index 702f131..c0ab25c 100644 +--- a/block/bsg.c ++++ b/block/bsg.c +@@ -985,7 +985,8 @@ void bsg_unregister_queue(struct request_queue *q) + + mutex_lock(&bsg_mutex); + idr_remove(&bsg_minor_idr, bcd->minor); +- sysfs_remove_link(&q->kobj, "bsg"); ++ if (q->kobj.sd) ++ sysfs_remove_link(&q->kobj, "bsg"); + device_unregister(bcd->class_dev); + bcd->class_dev = NULL; + kref_put(&bcd->ref, bsg_kref_release_function); +diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c +index 6d9a3ab..0a7ed69 100644 +--- a/drivers/acpi/sleep.c ++++ b/drivers/acpi/sleep.c +@@ -476,6 +476,22 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = { + DMI_MATCH(DMI_PRODUCT_NAME, "VGN-FW520F"), + }, + }, ++ { ++ .callback = init_nvs_nosave, ++ .ident = "Asus K54C", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), ++ DMI_MATCH(DMI_PRODUCT_NAME, "K54C"), ++ }, ++ }, ++ { ++ .callback = init_nvs_nosave, ++ .ident = "Asus K54HR", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), ++ DMI_MATCH(DMI_PRODUCT_NAME, "K54HR"), ++ }, ++ }, + {}, + }; + #endif /* CONFIG_SUSPEND */ +diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c +index dcd8bab..fe79635 100644 +--- a/drivers/crypto/mv_cesa.c ++++ b/drivers/crypto/mv_cesa.c +@@ -714,6 +714,7 @@ static int mv_hash_final(struct ahash_request *req) + { + struct mv_req_hash_ctx *ctx = ahash_request_ctx(req); + ++ ahash_request_set_crypt(req, NULL, req->result, 0); + mv_update_hash_req_ctx(ctx, 1, 0); + return mv_handle_req(&req->base); + } +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +index a26d5b0..1608d2a 100644 +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -2886,6 +2886,20 @@ + #define DISP_TILE_SURFACE_SWIZZLING (1<<13) + #define DISP_FBC_WM_DIS (1<<15) + ++/* GEN7 chicken */ ++#define GEN7_COMMON_SLICE_CHICKEN1 0x7010 ++# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) ++ ++#define GEN7_L3CNTLREG1 0xB01C ++#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C ++ ++#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 ++#define GEN7_WA_L3_CHICKEN_MODE 0x20000000 ++ ++/* WaCatErrorRejectionIssue */ ++#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 ++#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) ++ + /* PCH */ + + /* south display engine interrupt */ +@@ -3476,6 +3490,7 @@ + #define GT_FIFO_NUM_RESERVED_ENTRIES 20 + + #define GEN6_UCGCTL2 0x9404 ++# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) + # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) + # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) + +diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c +index daa5743..9ec9755 100644 +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -5876,14 +5876,14 @@ static void ironlake_write_eld(struct drm_connector *connector, + int aud_cntl_st; + int aud_cntrl_st2; + +- if (IS_IVYBRIDGE(connector->dev)) { +- hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A; +- aud_cntl_st = GEN7_AUD_CNTRL_ST_A; +- aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2; +- } else { ++ if (HAS_PCH_IBX(connector->dev)) { + hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A; + aud_cntl_st = GEN5_AUD_CNTL_ST_A; + aud_cntrl_st2 = GEN5_AUD_CNTL_ST2; ++ } else { ++ hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A; ++ aud_cntl_st = GEN7_AUD_CNTRL_ST_A; ++ aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2; + } + + i = to_intel_crtc(crtc)->pipe; +@@ -5965,7 +5965,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) + int i; + + /* The clocks have to be on to load the palette. */ +- if (!crtc->enabled) ++ if (!crtc->enabled || !intel_crtc->active) + return; + + /* use legacy palette for Ironlake */ +@@ -8248,8 +8248,28 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) + I915_WRITE(WM2_LP_ILK, 0); + I915_WRITE(WM1_LP_ILK, 0); + ++ /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. ++ * This implements the WaDisableRCZUnitClockGating workaround. ++ */ ++ I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); ++ + I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); + ++ /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ ++ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, ++ GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); ++ ++ /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ ++ I915_WRITE(GEN7_L3CNTLREG1, ++ GEN7_WA_FOR_GEN7_L3_CONTROL); ++ I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, ++ GEN7_WA_L3_CHICKEN_MODE); ++ ++ /* This is required by WaCatErrorRejectionIssue */ ++ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, ++ I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | ++ GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); ++ + for_each_pipe(pipe) { + I915_WRITE(DSPCNTR(pipe), + I915_READ(DSPCNTR(pipe)) | +diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c +index 2d1f6c5..73e2c7c 100644 +--- a/drivers/gpu/drm/radeon/r600_blit_shaders.c ++++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c +@@ -314,6 +314,10 @@ const u32 r6xx_default_state[] = + 0x00000000, /* VGT_VTX_CNT_EN */ + + 0xc0016900, ++ 0x000000d4, ++ 0x00000000, /* SX_MISC */ ++ ++ 0xc0016900, + 0x000002c8, + 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ + +@@ -626,6 +630,10 @@ const u32 r7xx_default_state[] = + 0x00000000, /* VGT_VTX_CNT_EN */ + + 0xc0016900, ++ 0x000000d4, ++ 0x00000000, /* SX_MISC */ ++ ++ 0xc0016900, + 0x000002c8, + 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ + +diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h +index 00cabb3..3c3daec 100644 +--- a/drivers/hid/hid-ids.h ++++ b/drivers/hid/hid-ids.h +@@ -59,6 +59,9 @@ + #define USB_VENDOR_ID_AIRCABLE 0x16CA + #define USB_DEVICE_ID_AIRCABLE1 0x1502 + ++#define USB_VENDOR_ID_AIREN 0x1a2c ++#define USB_DEVICE_ID_AIREN_SLIMPLUS 0x0002 ++ + #define USB_VENDOR_ID_ALCOR 0x058f + #define USB_DEVICE_ID_ALCOR_USBRS232 0x9720 + +diff --git a/drivers/hid/usbhid/hid-quirks.c b/drivers/hid/usbhid/hid-quirks.c +index 5028d60..1fe6b80 100644 +--- a/drivers/hid/usbhid/hid-quirks.c ++++ b/drivers/hid/usbhid/hid-quirks.c +@@ -53,6 +53,7 @@ static const struct hid_blacklist { + { USB_VENDOR_ID_PLAYDOTCOM, USB_DEVICE_ID_PLAYDOTCOM_EMS_USBII, HID_QUIRK_MULTI_INPUT }, + { USB_VENDOR_ID_TOUCHPACK, USB_DEVICE_ID_TOUCHPACK_RTS, HID_QUIRK_MULTI_INPUT }, + ++ { USB_VENDOR_ID_AIREN, USB_DEVICE_ID_AIREN_SLIMPLUS, HID_QUIRK_NOGET }, + { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_UC100KM, HID_QUIRK_NOGET }, + { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS124U, HID_QUIRK_NOGET }, + { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_2PORTKVM, HID_QUIRK_NOGET }, +diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig +index 91be41f..83e3e9d 100644 +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -497,8 +497,9 @@ config SENSORS_JC42 + If you say yes here, you get support for JEDEC JC42.4 compliant + temperature sensors, which are used on many DDR3 memory modules for + mobile devices and servers. Support will include, but not be limited +- to, ADT7408, CAT34TS02, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243, +- MCP9843, SE97, SE98, STTS424(E), TSE2002B3, and TS3000B3. ++ to, ADT7408, AT30TS00, CAT34TS02, CAT6095, MAX6604, MCP9804, MCP9805, ++ MCP98242, MCP98243, MCP9843, SE97, SE98, STTS424(E), STTS2002, ++ STTS3000, TSE2002B3, TSE2002GB2, TS3000B3, and TS3000GB2. + + This driver can also be built as a module. If so, the module + will be called jc42. +diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c +index 2d3d728..0274a05 100644 +--- a/drivers/hwmon/jc42.c ++++ b/drivers/hwmon/jc42.c +@@ -64,6 +64,7 @@ static const unsigned short normal_i2c[] = { + + /* Manufacturer IDs */ + #define ADT_MANID 0x11d4 /* Analog Devices */ ++#define ATMEL_MANID 0x001f /* Atmel */ + #define MAX_MANID 0x004d /* Maxim */ + #define IDT_MANID 0x00b3 /* IDT */ + #define MCP_MANID 0x0054 /* Microchip */ +@@ -77,15 +78,25 @@ static const unsigned short normal_i2c[] = { + #define ADT7408_DEVID 0x0801 + #define ADT7408_DEVID_MASK 0xffff + ++/* Atmel */ ++#define AT30TS00_DEVID 0x8201 ++#define AT30TS00_DEVID_MASK 0xffff ++ + /* IDT */ + #define TS3000B3_DEVID 0x2903 /* Also matches TSE2002B3 */ + #define TS3000B3_DEVID_MASK 0xffff + ++#define TS3000GB2_DEVID 0x2912 /* Also matches TSE2002GB2 */ ++#define TS3000GB2_DEVID_MASK 0xffff ++ + /* Maxim */ + #define MAX6604_DEVID 0x3e00 + #define MAX6604_DEVID_MASK 0xffff + + /* Microchip */ ++#define MCP9804_DEVID 0x0200 ++#define MCP9804_DEVID_MASK 0xfffc ++ + #define MCP98242_DEVID 0x2000 + #define MCP98242_DEVID_MASK 0xfffc + +@@ -113,6 +124,12 @@ static const unsigned short normal_i2c[] = { + #define STTS424E_DEVID 0x0000 + #define STTS424E_DEVID_MASK 0xfffe + ++#define STTS2002_DEVID 0x0300 ++#define STTS2002_DEVID_MASK 0xffff ++ ++#define STTS3000_DEVID 0x0200 ++#define STTS3000_DEVID_MASK 0xffff ++ + static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 }; + + struct jc42_chips { +@@ -123,8 +140,11 @@ struct jc42_chips { + + static struct jc42_chips jc42_chips[] = { + { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK }, ++ { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK }, + { IDT_MANID, TS3000B3_DEVID, TS3000B3_DEVID_MASK }, ++ { IDT_MANID, TS3000GB2_DEVID, TS3000GB2_DEVID_MASK }, + { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK }, ++ { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK }, + { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK }, + { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK }, + { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK }, +@@ -133,6 +153,8 @@ static struct jc42_chips jc42_chips[] = { + { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK }, + { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK }, + { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK }, ++ { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK }, ++ { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK }, + }; + + /* Each client has this additional data */ +@@ -159,10 +181,12 @@ static struct jc42_data *jc42_update_device(struct device *dev); + + static const struct i2c_device_id jc42_id[] = { + { "adt7408", 0 }, ++ { "at30ts00", 0 }, + { "cat94ts02", 0 }, + { "cat6095", 0 }, + { "jc42", 0 }, + { "max6604", 0 }, ++ { "mcp9804", 0 }, + { "mcp9805", 0 }, + { "mcp98242", 0 }, + { "mcp98243", 0 }, +@@ -171,8 +195,10 @@ static const struct i2c_device_id jc42_id[] = { + { "se97b", 0 }, + { "se98", 0 }, + { "stts424", 0 }, +- { "tse2002b3", 0 }, +- { "ts3000b3", 0 }, ++ { "stts2002", 0 }, ++ { "stts3000", 0 }, ++ { "tse2002", 0 }, ++ { "ts3000", 0 }, + { } + }; + MODULE_DEVICE_TABLE(i2c, jc42_id); +diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c +index 00460d8..d89b339 100644 +--- a/drivers/hwmon/pmbus/pmbus_core.c ++++ b/drivers/hwmon/pmbus/pmbus_core.c +@@ -54,7 +54,8 @@ + lcrit_alarm, crit_alarm */ + #define PMBUS_IOUT_BOOLEANS_PER_PAGE 3 /* alarm, lcrit_alarm, + crit_alarm */ +-#define PMBUS_POUT_BOOLEANS_PER_PAGE 2 /* alarm, crit_alarm */ ++#define PMBUS_POUT_BOOLEANS_PER_PAGE 3 /* cap_alarm, alarm, crit_alarm ++ */ + #define PMBUS_MAX_BOOLEANS_PER_FAN 2 /* alarm, fault */ + #define PMBUS_MAX_BOOLEANS_PER_TEMP 4 /* min_alarm, max_alarm, + lcrit_alarm, crit_alarm */ +diff --git a/drivers/hwmon/pmbus/zl6100.c b/drivers/hwmon/pmbus/zl6100.c +index 2bc9800..ba296fd 100644 +--- a/drivers/hwmon/pmbus/zl6100.c ++++ b/drivers/hwmon/pmbus/zl6100.c +@@ -33,6 +33,7 @@ enum chips { zl2004, zl2006, zl2008, zl2105, zl2106, zl6100, zl6105 }; + struct zl6100_data { + int id; + ktime_t access; /* chip access time */ ++ int delay; /* Delay between chip accesses in uS */ + struct pmbus_driver_info info; + }; + +@@ -49,10 +50,10 @@ MODULE_PARM_DESC(delay, "Delay between chip accesses in uS"); + /* Some chips need a delay between accesses */ + static inline void zl6100_wait(const struct zl6100_data *data) + { +- if (delay) { ++ if (data->delay) { + s64 delta = ktime_us_delta(ktime_get(), data->access); +- if (delta < delay) +- udelay(delay - delta); ++ if (delta < data->delay) ++ udelay(data->delay - delta); + } + } + +@@ -184,8 +185,9 @@ static int zl6100_probe(struct i2c_client *client, + * can be cleared later for additional chips if tests show that it + * is not needed (in other words, better be safe than sorry). + */ ++ data->delay = delay; + if (data->id == zl2004 || data->id == zl6105) +- delay = 0; ++ data->delay = 0; + + /* + * Since there was a direct I2C device access above, wait before +diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c +index 7e78f7c..3d471d5 100644 +--- a/drivers/i2c/busses/i2c-mxs.c ++++ b/drivers/i2c/busses/i2c-mxs.c +@@ -72,6 +72,7 @@ + + #define MXS_I2C_QUEUESTAT (0x70) + #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 ++#define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F + + #define MXS_I2C_QUEUECMD (0x80) + +@@ -219,14 +220,14 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, + int ret; + int flags; + +- init_completion(&i2c->cmd_complete); +- + dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", + msg->addr, msg->len, msg->flags, stop); + + if (msg->len == 0) + return -EINVAL; + ++ init_completion(&i2c->cmd_complete); ++ + flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; + + if (msg->flags & I2C_M_RD) +@@ -286,6 +287,7 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) + { + struct mxs_i2c_dev *i2c = dev_id; + u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; ++ bool is_last_cmd; + + if (!stat) + return IRQ_NONE; +@@ -300,9 +302,14 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) + else + i2c->cmd_err = 0; + +- complete(&i2c->cmd_complete); ++ is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) & ++ MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0; ++ ++ if (is_last_cmd || i2c->cmd_err) ++ complete(&i2c->cmd_complete); + + writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); ++ + return IRQ_HANDLED; + } + +diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c +index 003587c..9c40c11 100644 +--- a/drivers/input/mouse/alps.c ++++ b/drivers/input/mouse/alps.c +@@ -421,7 +421,9 @@ static const struct alps_model_info *alps_get_model(struct psmouse *psmouse, int + + /* + * First try "E6 report". +- * ALPS should return 0,0,10 or 0,0,100 ++ * ALPS should return 0,0,10 or 0,0,100 if no buttons are pressed. ++ * The bits 0-2 of the first byte will be 1s if some buttons are ++ * pressed. + */ + param[0] = 0; + if (ps2_command(ps2dev, param, PSMOUSE_CMD_SETRES) || +@@ -437,7 +439,8 @@ static const struct alps_model_info *alps_get_model(struct psmouse *psmouse, int + psmouse_dbg(psmouse, "E6 report: %2.2x %2.2x %2.2x", + param[0], param[1], param[2]); + +- if (param[0] != 0 || param[1] != 0 || (param[2] != 10 && param[2] != 100)) ++ if ((param[0] & 0xf8) != 0 || param[1] != 0 || ++ (param[2] != 10 && param[2] != 100)) + return NULL; + + /* +diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c +index 82d2410..5c74179 100644 +--- a/drivers/iommu/amd_iommu_init.c ++++ b/drivers/iommu/amd_iommu_init.c +@@ -268,7 +268,7 @@ static void iommu_set_exclusion_range(struct amd_iommu *iommu) + } + + /* Programs the physical address of the device table into the IOMMU hardware */ +-static void __init iommu_set_device_table(struct amd_iommu *iommu) ++static void iommu_set_device_table(struct amd_iommu *iommu) + { + u64 entry; + +diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c +index 8f32b2b..aba706c 100644 +--- a/drivers/iommu/omap-iommu.c ++++ b/drivers/iommu/omap-iommu.c +@@ -1229,7 +1229,8 @@ static int __init omap_iommu_init(void) + + return platform_driver_register(&omap_iommu_driver); + } +-module_init(omap_iommu_init); ++/* must be ready before omap3isp is probed */ ++subsys_initcall(omap_iommu_init); + + static void __exit omap_iommu_exit(void) + { +diff --git a/drivers/md/dm-flakey.c b/drivers/md/dm-flakey.c +index 9fb18c1..b280c43 100644 +--- a/drivers/md/dm-flakey.c ++++ b/drivers/md/dm-flakey.c +@@ -323,7 +323,7 @@ static int flakey_end_io(struct dm_target *ti, struct bio *bio, + * Corrupt successful READs while in down state. + * If flags were specified, only corrupt those that match. + */ +- if (!error && bio_submitted_while_down && ++ if (fc->corrupt_bio_byte && !error && bio_submitted_while_down && + (bio_data_dir(bio) == READ) && (fc->corrupt_bio_rw == READ) && + all_corrupt_bio_flags_match(bio, fc)) + corrupt_bio_data(bio, fc); +diff --git a/drivers/md/dm-io.c b/drivers/md/dm-io.c +index ad2eba4..ea5dd28 100644 +--- a/drivers/md/dm-io.c ++++ b/drivers/md/dm-io.c +@@ -296,6 +296,8 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where, + unsigned offset; + unsigned num_bvecs; + sector_t remaining = where->count; ++ struct request_queue *q = bdev_get_queue(where->bdev); ++ sector_t discard_sectors; + + /* + * where->count may be zero if rw holds a flush and we need to +@@ -305,9 +307,12 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where, + /* + * Allocate a suitably sized-bio. + */ +- num_bvecs = dm_sector_div_up(remaining, +- (PAGE_SIZE >> SECTOR_SHIFT)); +- num_bvecs = min_t(int, bio_get_nr_vecs(where->bdev), num_bvecs); ++ if (rw & REQ_DISCARD) ++ num_bvecs = 1; ++ else ++ num_bvecs = min_t(int, bio_get_nr_vecs(where->bdev), ++ dm_sector_div_up(remaining, (PAGE_SIZE >> SECTOR_SHIFT))); ++ + bio = bio_alloc_bioset(GFP_NOIO, num_bvecs, io->client->bios); + bio->bi_sector = where->sector + (where->count - remaining); + bio->bi_bdev = where->bdev; +@@ -315,10 +320,14 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where, + bio->bi_destructor = dm_bio_destructor; + store_io_and_region_in_bio(bio, io, region); + +- /* +- * Try and add as many pages as possible. +- */ +- while (remaining) { ++ if (rw & REQ_DISCARD) { ++ discard_sectors = min_t(sector_t, q->limits.max_discard_sectors, remaining); ++ bio->bi_size = discard_sectors << SECTOR_SHIFT; ++ remaining -= discard_sectors; ++ } else while (remaining) { ++ /* ++ * Try and add as many pages as possible. ++ */ + dp->get_page(dp, &page, &len, &offset); + len = min(len, to_bytes(remaining)); + if (!bio_add_page(bio, page, len, offset)) +diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c +index 31c2dc2..1ce84ed 100644 +--- a/drivers/md/dm-ioctl.c ++++ b/drivers/md/dm-ioctl.c +@@ -1437,7 +1437,7 @@ static int target_message(struct dm_ioctl *param, size_t param_size) + + if (!argc) { + DMWARN("Empty message received."); +- goto out; ++ goto out_argv; + } + + table = dm_get_live_table(md); +diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c +index c2907d8..d2a3223 100644 +--- a/drivers/md/dm-raid.c ++++ b/drivers/md/dm-raid.c +@@ -667,7 +667,14 @@ static int super_load(struct md_rdev *rdev, struct md_rdev *refdev) + return ret; + + sb = page_address(rdev->sb_page); +- if (sb->magic != cpu_to_le32(DM_RAID_MAGIC)) { ++ ++ /* ++ * Two cases that we want to write new superblocks and rebuild: ++ * 1) New device (no matching magic number) ++ * 2) Device specified for rebuild (!In_sync w/ offset == 0) ++ */ ++ if ((sb->magic != cpu_to_le32(DM_RAID_MAGIC)) || ++ (!test_bit(In_sync, &rdev->flags) && !rdev->recovery_offset)) { + super_sync(rdev->mddev, rdev); + + set_bit(FirstUse, &rdev->flags); +@@ -744,11 +751,8 @@ static int super_init_validation(struct mddev *mddev, struct md_rdev *rdev) + */ + rdev_for_each(r, t, mddev) { + if (!test_bit(In_sync, &r->flags)) { +- if (!test_bit(FirstUse, &r->flags)) +- DMERR("Superblock area of " +- "rebuild device %d should have been " +- "cleared.", r->raid_disk); +- set_bit(FirstUse, &r->flags); ++ DMINFO("Device %d specified for rebuild: " ++ "Clearing superblock", r->raid_disk); + rebuilds++; + } else if (test_bit(FirstUse, &r->flags)) + new_devs++; +@@ -970,6 +974,7 @@ static int raid_ctr(struct dm_target *ti, unsigned argc, char **argv) + + INIT_WORK(&rs->md.event_work, do_table_event); + ti->private = rs; ++ ti->num_flush_requests = 1; + + mutex_lock(&rs->md.reconfig_mutex); + ret = md_run(&rs->md); +diff --git a/drivers/md/dm-thin-metadata.c b/drivers/md/dm-thin-metadata.c +index 59c4f04..237571a 100644 +--- a/drivers/md/dm-thin-metadata.c ++++ b/drivers/md/dm-thin-metadata.c +@@ -385,6 +385,7 @@ static int init_pmd(struct dm_pool_metadata *pmd, + data_sm = dm_sm_disk_create(tm, nr_blocks); + if (IS_ERR(data_sm)) { + DMERR("sm_disk_create failed"); ++ dm_tm_unlock(tm, sblock); + r = PTR_ERR(data_sm); + goto bad; + } +@@ -789,6 +790,11 @@ int dm_pool_metadata_close(struct dm_pool_metadata *pmd) + return 0; + } + ++/* ++ * __open_device: Returns @td corresponding to device with id @dev, ++ * creating it if @create is set and incrementing @td->open_count. ++ * On failure, @td is undefined. ++ */ + static int __open_device(struct dm_pool_metadata *pmd, + dm_thin_id dev, int create, + struct dm_thin_device **td) +@@ -799,10 +805,16 @@ static int __open_device(struct dm_pool_metadata *pmd, + struct disk_device_details details_le; + + /* +- * Check the device isn't already open. ++ * If the device is already open, return it. + */ + list_for_each_entry(td2, &pmd->thin_devices, list) + if (td2->id == dev) { ++ /* ++ * May not create an already-open device. ++ */ ++ if (create) ++ return -EEXIST; ++ + td2->open_count++; + *td = td2; + return 0; +@@ -817,6 +829,9 @@ static int __open_device(struct dm_pool_metadata *pmd, + if (r != -ENODATA || !create) + return r; + ++ /* ++ * Create new device. ++ */ + changed = 1; + details_le.mapped_blocks = 0; + details_le.transaction_id = cpu_to_le64(pmd->trans_id); +@@ -882,12 +897,10 @@ static int __create_thin(struct dm_pool_metadata *pmd, + + r = __open_device(pmd, dev, 1, &td); + if (r) { +- __close_device(td); + dm_btree_remove(&pmd->tl_info, pmd->root, &key, &pmd->root); + dm_btree_del(&pmd->bl_info, dev_root); + return r; + } +- td->changed = 1; + __close_device(td); + + return r; +@@ -967,14 +980,14 @@ static int __create_snap(struct dm_pool_metadata *pmd, + goto bad; + + r = __set_snapshot_details(pmd, td, origin, pmd->time); ++ __close_device(td); ++ + if (r) + goto bad; + +- __close_device(td); + return 0; + + bad: +- __close_device(td); + dm_btree_remove(&pmd->tl_info, pmd->root, &key, &pmd->root); + dm_btree_remove(&pmd->details_info, pmd->details_root, + &key, &pmd->details_root); +@@ -1211,6 +1224,8 @@ static int __remove(struct dm_thin_device *td, dm_block_t block) + if (r) + return r; + ++ td->mapped_blocks--; ++ td->changed = 1; + pmd->need_commit = 1; + + return 0; +diff --git a/drivers/mfd/cs5535-mfd.c b/drivers/mfd/cs5535-mfd.c +index 155fa04..e488a78 100644 +--- a/drivers/mfd/cs5535-mfd.c ++++ b/drivers/mfd/cs5535-mfd.c +@@ -179,7 +179,7 @@ static struct pci_device_id cs5535_mfd_pci_tbl[] = { + }; + MODULE_DEVICE_TABLE(pci, cs5535_mfd_pci_tbl); + +-static struct pci_driver cs5535_mfd_drv = { ++static struct pci_driver cs5535_mfd_driver = { + .name = DRV_NAME, + .id_table = cs5535_mfd_pci_tbl, + .probe = cs5535_mfd_probe, +@@ -188,12 +188,12 @@ static struct pci_driver cs5535_mfd_drv = { + + static int __init cs5535_mfd_init(void) + { +- return pci_register_driver(&cs5535_mfd_drv); ++ return pci_register_driver(&cs5535_mfd_driver); + } + + static void __exit cs5535_mfd_exit(void) + { +- pci_unregister_driver(&cs5535_mfd_drv); ++ pci_unregister_driver(&cs5535_mfd_driver); + } + + module_init(cs5535_mfd_init); +diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c +index 0f59228..411f523 100644 +--- a/drivers/mfd/mfd-core.c ++++ b/drivers/mfd/mfd-core.c +@@ -123,7 +123,7 @@ static int mfd_add_device(struct device *parent, int id, + } + + if (!cell->ignore_resource_conflicts) { +- ret = acpi_check_resource_conflict(res); ++ ret = acpi_check_resource_conflict(&res[r]); + if (ret) + goto fail_res; + } +diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c +index 61894fc..9302d21 100644 +--- a/drivers/mfd/wm8994-core.c ++++ b/drivers/mfd/wm8994-core.c +@@ -252,6 +252,20 @@ static int wm8994_suspend(struct device *dev) + break; + } + ++ switch (wm8994->type) { ++ case WM1811: ++ ret = wm8994_reg_read(wm8994, WM8994_ANTIPOP_2); ++ if (ret < 0) { ++ dev_err(dev, "Failed to read jackdet: %d\n", ret); ++ } else if (ret & WM1811_JACKDET_MODE_MASK) { ++ dev_dbg(dev, "CODEC still active, ignoring suspend\n"); ++ return 0; ++ } ++ break; ++ default: ++ break; ++ } ++ + /* Disable LDO pulldowns while the device is suspended if we + * don't know that something will be driving them. */ + if (!wm8994->ldo_ena_always_driven) +diff --git a/drivers/misc/cs5535-mfgpt.c b/drivers/misc/cs5535-mfgpt.c +index bc685bf..87a390d 100644 +--- a/drivers/misc/cs5535-mfgpt.c ++++ b/drivers/misc/cs5535-mfgpt.c +@@ -262,7 +262,7 @@ static void __init reset_all_timers(void) + * In other cases (such as with VSAless OpenFirmware), the system firmware + * leaves timers available for us to use. + */ +-static int __init scan_timers(struct cs5535_mfgpt_chip *mfgpt) ++static int __devinit scan_timers(struct cs5535_mfgpt_chip *mfgpt) + { + struct cs5535_mfgpt_timer timer = { .chip = mfgpt }; + unsigned long flags; +diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c +index 72bc756..9896933 100644 +--- a/drivers/mmc/host/atmel-mci.c ++++ b/drivers/mmc/host/atmel-mci.c +@@ -1944,12 +1944,12 @@ static bool atmci_filter(struct dma_chan *chan, void *slave) + } + } + +-static void atmci_configure_dma(struct atmel_mci *host) ++static bool atmci_configure_dma(struct atmel_mci *host) + { + struct mci_platform_data *pdata; + + if (host == NULL) +- return; ++ return false; + + pdata = host->pdev->dev.platform_data; + +@@ -1966,12 +1966,15 @@ static void atmci_configure_dma(struct atmel_mci *host) + host->dma.chan = + dma_request_channel(mask, atmci_filter, pdata->dma_slave); + } +- if (!host->dma.chan) +- dev_notice(&host->pdev->dev, "DMA not available, using PIO\n"); +- else ++ if (!host->dma.chan) { ++ dev_warn(&host->pdev->dev, "no DMA channel available\n"); ++ return false; ++ } else { + dev_info(&host->pdev->dev, + "Using %s for DMA transfers\n", + dma_chan_name(host->dma.chan)); ++ return true; ++ } + } + + static inline unsigned int atmci_get_version(struct atmel_mci *host) +@@ -2081,8 +2084,7 @@ static int __init atmci_probe(struct platform_device *pdev) + + /* Get MCI capabilities and set operations according to it */ + atmci_get_cap(host); +- if (host->caps.has_dma) { +- dev_info(&pdev->dev, "using DMA\n"); ++ if (host->caps.has_dma && atmci_configure_dma(host)) { + host->prepare_data = &atmci_prepare_data_dma; + host->submit_data = &atmci_submit_data_dma; + host->stop_transfer = &atmci_stop_transfer_dma; +@@ -2092,15 +2094,12 @@ static int __init atmci_probe(struct platform_device *pdev) + host->submit_data = &atmci_submit_data_pdc; + host->stop_transfer = &atmci_stop_transfer_pdc; + } else { +- dev_info(&pdev->dev, "no DMA, no PDC\n"); ++ dev_info(&pdev->dev, "using PIO\n"); + host->prepare_data = &atmci_prepare_data; + host->submit_data = &atmci_submit_data; + host->stop_transfer = &atmci_stop_transfer; + } + +- if (host->caps.has_dma) +- atmci_configure_dma(host); +- + platform_set_drvdata(pdev, host); + + /* We need at least one slot to succeed */ +diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c +index 38ebc4e..4540e37 100644 +--- a/drivers/mmc/host/sdhci-esdhc-imx.c ++++ b/drivers/mmc/host/sdhci-esdhc-imx.c +@@ -269,8 +269,9 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) + imx_data->scratchpad = val; + return; + case SDHCI_COMMAND: +- if ((host->cmd->opcode == MMC_STOP_TRANSMISSION) +- && (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) ++ if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || ++ host->cmd->opcode == MMC_SET_BLOCK_COUNT) && ++ (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) + val |= SDHCI_CMD_ABORTCMD; + + if (is_imx6q_usdhc(imx_data)) { +diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c +index 99ed6eb..4fd4144 100644 +--- a/drivers/net/usb/cdc_ether.c ++++ b/drivers/net/usb/cdc_ether.c +@@ -570,6 +570,13 @@ static const struct usb_device_id products [] = { + .driver_info = 0, + }, + ++/* Logitech Harmony 900 - uses the pseudo-MDLM (BLAN) driver */ ++{ ++ USB_DEVICE_AND_INTERFACE_INFO(0x046d, 0xc11f, USB_CLASS_COMM, ++ USB_CDC_SUBCLASS_MDLM, USB_CDC_PROTO_NONE), ++ .driver_info = 0, ++}, ++ + /* + * WHITELIST!!! + * +diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c +index fae0fbd..81b96e3 100644 +--- a/drivers/net/usb/usbnet.c ++++ b/drivers/net/usb/usbnet.c +@@ -589,6 +589,7 @@ static int unlink_urbs (struct usbnet *dev, struct sk_buff_head *q) + entry = (struct skb_data *) skb->cb; + urb = entry->urb; + ++ spin_unlock_irqrestore(&q->lock, flags); + // during some PM-driven resume scenarios, + // these (async) unlinks complete immediately + retval = usb_unlink_urb (urb); +@@ -596,6 +597,7 @@ static int unlink_urbs (struct usbnet *dev, struct sk_buff_head *q) + netdev_dbg(dev->net, "unlink urb err, %d\n", retval); + else + count++; ++ spin_lock_irqsave(&q->lock, flags); + } + spin_unlock_irqrestore (&q->lock, flags); + return count; +diff --git a/drivers/net/usb/zaurus.c b/drivers/net/usb/zaurus.c +index 1a2234c..246b3bb 100644 +--- a/drivers/net/usb/zaurus.c ++++ b/drivers/net/usb/zaurus.c +@@ -349,6 +349,13 @@ static const struct usb_device_id products [] = { + ZAURUS_MASTER_INTERFACE, + .driver_info = OLYMPUS_MXL_INFO, + }, ++ ++/* Logitech Harmony 900 - uses the pseudo-MDLM (BLAN) driver */ ++{ ++ USB_DEVICE_AND_INTERFACE_INFO(0x046d, 0xc11f, USB_CLASS_COMM, ++ USB_CDC_SUBCLASS_MDLM, USB_CDC_PROTO_NONE), ++ .driver_info = (unsigned long) &bogus_mdlm_info, ++}, + { }, // END + }; + MODULE_DEVICE_TABLE(usb, products); +diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c +index f199e9e..0a3c7c8 100644 +--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c ++++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c +@@ -489,8 +489,6 @@ static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) + ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows); + ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows); + ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows); +- ATH_ALLOC_BANK(ah->addac5416_21, +- ah->iniAddac.ia_rows * ah->iniAddac.ia_columns); + ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows); + + return 0; +@@ -519,7 +517,6 @@ static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah) + ATH_FREE_BANK(ah->analogBank6Data); + ATH_FREE_BANK(ah->analogBank6TPCData); + ATH_FREE_BANK(ah->analogBank7Data); +- ATH_FREE_BANK(ah->addac5416_21); + ATH_FREE_BANK(ah->bank6Temp); + + #undef ATH_FREE_BANK +@@ -805,27 +802,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, + if (ah->eep_ops->set_addac) + ah->eep_ops->set_addac(ah, chan); + +- if (AR_SREV_5416_22_OR_LATER(ah)) { +- REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); +- } else { +- struct ar5416IniArray temp; +- u32 addacSize = +- sizeof(u32) * ah->iniAddac.ia_rows * +- ah->iniAddac.ia_columns; +- +- /* For AR5416 2.0/2.1 */ +- memcpy(ah->addac5416_21, +- ah->iniAddac.ia_array, addacSize); +- +- /* override CLKDRV value at [row, column] = [31, 1] */ +- (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; +- +- temp.ia_array = ah->addac5416_21; +- temp.ia_columns = ah->iniAddac.ia_columns; +- temp.ia_rows = ah->iniAddac.ia_rows; +- REG_WRITE_ARRAY(&temp, 1, regWrites); +- } +- ++ REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); + + ENABLE_REGWRITE_BUFFER(ah); +diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c +index 11f192a..d190411 100644 +--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c ++++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c +@@ -180,6 +180,25 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, + ARRAY_SIZE(ar5416Addac), 2); + } ++ ++ /* iniAddac needs to be modified for these chips */ ++ if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) { ++ struct ar5416IniArray *addac = &ah->iniAddac; ++ u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns; ++ u32 *data; ++ ++ data = kmalloc(size, GFP_KERNEL); ++ if (!data) ++ return; ++ ++ memcpy(data, addac->ia_array, size); ++ addac->ia_array = data; ++ ++ if (!AR_SREV_5416_22_OR_LATER(ah)) { ++ /* override CLKDRV value */ ++ INI_RA(addac, 31,1) = 0; ++ } ++ } + } + + /* Support for Japan ch.14 (2484) spread */ +diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h +index f389b3c..1bd8edf 100644 +--- a/drivers/net/wireless/ath/ath9k/hw.h ++++ b/drivers/net/wireless/ath/ath9k/hw.h +@@ -772,7 +772,6 @@ struct ath_hw { + u32 *analogBank6Data; + u32 *analogBank6TPCData; + u32 *analogBank7Data; +- u32 *addac5416_21; + u32 *bank6Temp; + + u8 txpower_limit; +diff --git a/drivers/net/wireless/ath/carl9170/tx.c b/drivers/net/wireless/ath/carl9170/tx.c +index 59472e1..f6384af 100644 +--- a/drivers/net/wireless/ath/carl9170/tx.c ++++ b/drivers/net/wireless/ath/carl9170/tx.c +@@ -1234,6 +1234,7 @@ static bool carl9170_tx_ps_drop(struct ar9170 *ar, struct sk_buff *skb) + { + struct ieee80211_sta *sta; + struct carl9170_sta_info *sta_info; ++ struct ieee80211_tx_info *tx_info; + + rcu_read_lock(); + sta = __carl9170_get_tx_sta(ar, skb); +@@ -1241,16 +1242,18 @@ static bool carl9170_tx_ps_drop(struct ar9170 *ar, struct sk_buff *skb) + goto out_rcu; + + sta_info = (void *) sta->drv_priv; +- if (unlikely(sta_info->sleeping)) { +- struct ieee80211_tx_info *tx_info; ++ tx_info = IEEE80211_SKB_CB(skb); + ++ if (unlikely(sta_info->sleeping) && ++ !(tx_info->flags & (IEEE80211_TX_CTL_POLL_RESPONSE | ++ IEEE80211_TX_CTL_CLEAR_PS_FILT))) { + rcu_read_unlock(); + +- tx_info = IEEE80211_SKB_CB(skb); + if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) + atomic_dec(&ar->tx_ampdu_upload); + + tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; ++ carl9170_release_dev_space(ar, skb); + carl9170_tx_status(ar, skb, false); + return true; + } +diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-sta.c b/drivers/net/wireless/iwlwifi/iwl-agn-sta.c +index 4b2aa1d..5cfb3d1 100644 +--- a/drivers/net/wireless/iwlwifi/iwl-agn-sta.c ++++ b/drivers/net/wireless/iwlwifi/iwl-agn-sta.c +@@ -1211,6 +1211,7 @@ int iwl_remove_dynamic_key(struct iwl_priv *priv, + unsigned long flags; + struct iwl_addsta_cmd sta_cmd; + u8 sta_id = iwlagn_key_sta_id(priv, ctx->vif, sta); ++ __le16 key_flags; + + /* if station isn't there, neither is the key */ + if (sta_id == IWL_INVALID_STATION) +@@ -1236,7 +1237,14 @@ int iwl_remove_dynamic_key(struct iwl_priv *priv, + IWL_ERR(priv, "offset %d not used in uCode key table.\n", + keyconf->hw_key_idx); + +- sta_cmd.key.key_flags = STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID; ++ key_flags = cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); ++ key_flags |= STA_KEY_FLG_MAP_KEY_MSK | STA_KEY_FLG_NO_ENC | ++ STA_KEY_FLG_INVALID; ++ ++ if (!(keyconf->flags & IEEE80211_KEY_FLAG_PAIRWISE)) ++ key_flags |= STA_KEY_MULTICAST_MSK; ++ ++ sta_cmd.key.key_flags = key_flags; + sta_cmd.key.key_offset = WEP_INVALID_OFFSET; + sta_cmd.sta.modify_mask = STA_MODIFY_KEY_MASK; + sta_cmd.mode = STA_CONTROL_MODIFY_MSK; +diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c +index c244f2f..94a3e17 100644 +--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c ++++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c +@@ -275,6 +275,8 @@ static struct usb_device_id rtl8192c_usb_ids[] = { + {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8191, rtl92cu_hal_cfg)}, + + /****** 8188CU ********/ ++ /* RTL8188CTV */ ++ {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x018a, rtl92cu_hal_cfg)}, + /* 8188CE-VAU USB minCard */ + {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8170, rtl92cu_hal_cfg)}, + /* 8188cu 1*1 dongle */ +@@ -291,14 +293,14 @@ static struct usb_device_id rtl8192c_usb_ids[] = { + {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817e, rtl92cu_hal_cfg)}, + /* 8188RU in Alfa AWUS036NHR */ + {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817f, rtl92cu_hal_cfg)}, ++ /* RTL8188CUS-VL */ ++ {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x818a, rtl92cu_hal_cfg)}, + /* 8188 Combo for BC4 */ + {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8754, rtl92cu_hal_cfg)}, + + /****** 8192CU ********/ +- /* 8191cu 1*2 */ +- {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8177, rtl92cu_hal_cfg)}, + /* 8192cu 2*2 */ +- {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817b, rtl92cu_hal_cfg)}, ++ {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8178, rtl92cu_hal_cfg)}, + /* 8192CE-VAU USB minCard */ + {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817c, rtl92cu_hal_cfg)}, + +@@ -309,13 +311,17 @@ static struct usb_device_id rtl8192c_usb_ids[] = { + {RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/ + {RTL_USB_DEVICE(0x07b8, 0x8189, rtl92cu_hal_cfg)}, /*Funai - Abocom*/ + {RTL_USB_DEVICE(0x0846, 0x9041, rtl92cu_hal_cfg)}, /*NetGear WNA1000M*/ +- {RTL_USB_DEVICE(0x0Df6, 0x0052, rtl92cu_hal_cfg)}, /*Sitecom - Edimax*/ ++ {RTL_USB_DEVICE(0x0df6, 0x0052, rtl92cu_hal_cfg)}, /*Sitecom - Edimax*/ ++ {RTL_USB_DEVICE(0x0df6, 0x005c, rtl92cu_hal_cfg)}, /*Sitecom - Edimax*/ + {RTL_USB_DEVICE(0x0eb0, 0x9071, rtl92cu_hal_cfg)}, /*NO Brand - Etop*/ + /* HP - Lite-On ,8188CUS Slim Combo */ + {RTL_USB_DEVICE(0x103c, 0x1629, rtl92cu_hal_cfg)}, + {RTL_USB_DEVICE(0x13d3, 0x3357, rtl92cu_hal_cfg)}, /* AzureWave */ + {RTL_USB_DEVICE(0x2001, 0x3308, rtl92cu_hal_cfg)}, /*D-Link - Alpha*/ ++ {RTL_USB_DEVICE(0x2019, 0x4902, rtl92cu_hal_cfg)}, /*Planex - Etop*/ + {RTL_USB_DEVICE(0x2019, 0xab2a, rtl92cu_hal_cfg)}, /*Planex - Abocom*/ ++ /*SW-WF02-AD15 -Abocom*/ ++ {RTL_USB_DEVICE(0x2019, 0xab2e, rtl92cu_hal_cfg)}, + {RTL_USB_DEVICE(0x2019, 0xed17, rtl92cu_hal_cfg)}, /*PCI - Edimax*/ + {RTL_USB_DEVICE(0x20f4, 0x648b, rtl92cu_hal_cfg)}, /*TRENDnet - Cameo*/ + {RTL_USB_DEVICE(0x7392, 0x7811, rtl92cu_hal_cfg)}, /*Edimax - Edimax*/ +@@ -326,14 +332,36 @@ static struct usb_device_id rtl8192c_usb_ids[] = { + {RTL_USB_DEVICE(0x4855, 0x0091, rtl92cu_hal_cfg)}, /* NetweeN-Feixun */ + {RTL_USB_DEVICE(0x9846, 0x9041, rtl92cu_hal_cfg)}, /* Netgear Cameo */ + ++ /****** 8188 RU ********/ ++ /* Netcore */ ++ {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x317f, rtl92cu_hal_cfg)}, ++ ++ /****** 8188CUS Slim Solo********/ ++ {RTL_USB_DEVICE(0x04f2, 0xaff7, rtl92cu_hal_cfg)}, /*Xavi*/ ++ {RTL_USB_DEVICE(0x04f2, 0xaff9, rtl92cu_hal_cfg)}, /*Xavi*/ ++ {RTL_USB_DEVICE(0x04f2, 0xaffa, rtl92cu_hal_cfg)}, /*Xavi*/ ++ ++ /****** 8188CUS Slim Combo ********/ ++ {RTL_USB_DEVICE(0x04f2, 0xaff8, rtl92cu_hal_cfg)}, /*Xavi*/ ++ {RTL_USB_DEVICE(0x04f2, 0xaffb, rtl92cu_hal_cfg)}, /*Xavi*/ ++ {RTL_USB_DEVICE(0x04f2, 0xaffc, rtl92cu_hal_cfg)}, /*Xavi*/ ++ {RTL_USB_DEVICE(0x2019, 0x1201, rtl92cu_hal_cfg)}, /*Planex-Vencer*/ ++ + /****** 8192CU ********/ ++ {RTL_USB_DEVICE(0x050d, 0x2102, rtl92cu_hal_cfg)}, /*Belcom-Sercomm*/ ++ {RTL_USB_DEVICE(0x050d, 0x2103, rtl92cu_hal_cfg)}, /*Belcom-Edimax*/ + {RTL_USB_DEVICE(0x0586, 0x341f, rtl92cu_hal_cfg)}, /*Zyxel -Abocom*/ + {RTL_USB_DEVICE(0x07aa, 0x0056, rtl92cu_hal_cfg)}, /*ATKK-Gemtek*/ + {RTL_USB_DEVICE(0x07b8, 0x8178, rtl92cu_hal_cfg)}, /*Funai -Abocom*/ ++ {RTL_USB_DEVICE(0x0846, 0x9021, rtl92cu_hal_cfg)}, /*Netgear-Sercomm*/ ++ {RTL_USB_DEVICE(0x0b05, 0x17ab, rtl92cu_hal_cfg)}, /*ASUS-Edimax*/ ++ {RTL_USB_DEVICE(0x0df6, 0x0061, rtl92cu_hal_cfg)}, /*Sitecom-Edimax*/ ++ {RTL_USB_DEVICE(0x0e66, 0x0019, rtl92cu_hal_cfg)}, /*Hawking-Edimax*/ + {RTL_USB_DEVICE(0x2001, 0x3307, rtl92cu_hal_cfg)}, /*D-Link-Cameo*/ + {RTL_USB_DEVICE(0x2001, 0x3309, rtl92cu_hal_cfg)}, /*D-Link-Alpha*/ + {RTL_USB_DEVICE(0x2001, 0x330a, rtl92cu_hal_cfg)}, /*D-Link-Alpha*/ + {RTL_USB_DEVICE(0x2019, 0xab2b, rtl92cu_hal_cfg)}, /*Planex -Abocom*/ ++ {RTL_USB_DEVICE(0x20f4, 0x624d, rtl92cu_hal_cfg)}, /*TRENDNet*/ + {RTL_USB_DEVICE(0x7392, 0x7822, rtl92cu_hal_cfg)}, /*Edimax -Edimax*/ + {} + }; +diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c +index 691b1ab..30d2072 100644 +--- a/drivers/rapidio/devices/tsi721.c ++++ b/drivers/rapidio/devices/tsi721.c +@@ -410,13 +410,14 @@ static void tsi721_db_dpc(struct work_struct *work) + */ + mport = priv->mport; + +- wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)); +- rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)); ++ wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; ++ rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE; + + while (wr_ptr != rd_ptr) { + idb_entry = (u64 *)(priv->idb_base + + (TSI721_IDB_ENTRY_SIZE * rd_ptr)); + rd_ptr++; ++ rd_ptr %= IDB_QSIZE; + idb.msg = *idb_entry; + *idb_entry = 0; + +diff --git a/drivers/regulator/88pm8607.c b/drivers/regulator/88pm8607.c +index ca0d608..1cead1d 100644 +--- a/drivers/regulator/88pm8607.c ++++ b/drivers/regulator/88pm8607.c +@@ -196,7 +196,7 @@ static const unsigned int LDO12_suspend_table[] = { + }; + + static const unsigned int LDO13_table[] = { +- 1300000, 1800000, 2000000, 2500000, 2800000, 3000000, 0, 0, ++ 1200000, 1300000, 1800000, 2000000, 2500000, 2800000, 3000000, 0, + }; + + static const unsigned int LDO13_suspend_table[] = { +@@ -389,10 +389,10 @@ static struct pm8607_regulator_info pm8607_regulator_info[] = { + PM8607_LDO( 7, LDO7, 0, 3, SUPPLIES_EN12, 1), + PM8607_LDO( 8, LDO8, 0, 3, SUPPLIES_EN12, 2), + PM8607_LDO( 9, LDO9, 0, 3, SUPPLIES_EN12, 3), +- PM8607_LDO(10, LDO10, 0, 3, SUPPLIES_EN12, 4), ++ PM8607_LDO(10, LDO10, 0, 4, SUPPLIES_EN12, 4), + PM8607_LDO(12, LDO12, 0, 4, SUPPLIES_EN12, 5), + PM8607_LDO(13, VIBRATOR_SET, 1, 3, VIBRATOR_SET, 0), +- PM8607_LDO(14, LDO14, 0, 4, SUPPLIES_EN12, 6), ++ PM8607_LDO(14, LDO14, 0, 3, SUPPLIES_EN12, 6), + }; + + static int __devinit pm8607_regulator_probe(struct platform_device *pdev) +diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c +index 6ab2968..fe9dacc 100644 +--- a/drivers/s390/block/dasd_eckd.c ++++ b/drivers/s390/block/dasd_eckd.c +@@ -18,12 +18,12 @@ + #include <linux/hdreg.h> /* HDIO_GETGEO */ + #include <linux/bio.h> + #include <linux/module.h> ++#include <linux/compat.h> + #include <linux/init.h> + + #include <asm/debug.h> + #include <asm/idals.h> + #include <asm/ebcdic.h> +-#include <asm/compat.h> + #include <asm/io.h> + #include <asm/uaccess.h> + #include <asm/cio.h> +diff --git a/drivers/s390/block/dasd_ioctl.c b/drivers/s390/block/dasd_ioctl.c +index f1a2016..792c69e 100644 +--- a/drivers/s390/block/dasd_ioctl.c ++++ b/drivers/s390/block/dasd_ioctl.c +@@ -13,6 +13,7 @@ + #define KMSG_COMPONENT "dasd" + + #include <linux/interrupt.h> ++#include <linux/compat.h> + #include <linux/major.h> + #include <linux/fs.h> + #include <linux/blkpg.h> +diff --git a/drivers/s390/char/fs3270.c b/drivers/s390/char/fs3270.c +index e712981..9117045 100644 +--- a/drivers/s390/char/fs3270.c ++++ b/drivers/s390/char/fs3270.c +@@ -11,6 +11,7 @@ + #include <linux/console.h> + #include <linux/init.h> + #include <linux/interrupt.h> ++#include <linux/compat.h> + #include <linux/module.h> + #include <linux/list.h> + #include <linux/slab.h> +diff --git a/drivers/s390/char/vmcp.c b/drivers/s390/char/vmcp.c +index 75bde6a..89c03e6 100644 +--- a/drivers/s390/char/vmcp.c ++++ b/drivers/s390/char/vmcp.c +@@ -13,6 +13,7 @@ + + #include <linux/fs.h> + #include <linux/init.h> ++#include <linux/compat.h> + #include <linux/kernel.h> + #include <linux/miscdevice.h> + #include <linux/slab.h> +diff --git a/drivers/s390/cio/chsc_sch.c b/drivers/s390/cio/chsc_sch.c +index 0c87b0f..8f9a1a3 100644 +--- a/drivers/s390/cio/chsc_sch.c ++++ b/drivers/s390/cio/chsc_sch.c +@@ -8,6 +8,7 @@ + */ + + #include <linux/slab.h> ++#include <linux/compat.h> + #include <linux/device.h> + #include <linux/module.h> + #include <linux/uaccess.h> +diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c +index 3ef8d07..770a740 100644 +--- a/drivers/s390/cio/qdio_main.c ++++ b/drivers/s390/cio/qdio_main.c +@@ -167,7 +167,7 @@ again: + DBF_ERROR("%4x EQBS ERROR", SCH_NO(q)); + DBF_ERROR("%3d%3d%2d", count, tmp_count, nr); + q->handler(q->irq_ptr->cdev, QDIO_ERROR_ACTIVATE_CHECK_CONDITION, +- 0, -1, -1, q->irq_ptr->int_parm); ++ q->nr, q->first_to_kick, count, q->irq_ptr->int_parm); + return 0; + } + +@@ -215,7 +215,7 @@ again: + DBF_ERROR("%4x SQBS ERROR", SCH_NO(q)); + DBF_ERROR("%3d%3d%2d", count, tmp_count, nr); + q->handler(q->irq_ptr->cdev, QDIO_ERROR_ACTIVATE_CHECK_CONDITION, +- 0, -1, -1, q->irq_ptr->int_parm); ++ q->nr, q->first_to_kick, count, q->irq_ptr->int_parm); + return 0; + } + +diff --git a/drivers/s390/scsi/zfcp_cfdc.c b/drivers/s390/scsi/zfcp_cfdc.c +index 303dde0..fab2c25 100644 +--- a/drivers/s390/scsi/zfcp_cfdc.c ++++ b/drivers/s390/scsi/zfcp_cfdc.c +@@ -11,6 +11,7 @@ + #define KMSG_COMPONENT "zfcp" + #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt + ++#include <linux/compat.h> + #include <linux/slab.h> + #include <linux/types.h> + #include <linux/miscdevice.h> +diff --git a/drivers/scsi/osd/osd_uld.c b/drivers/scsi/osd/osd_uld.c +index b31a8e3..d4ed9eb 100644 +--- a/drivers/scsi/osd/osd_uld.c ++++ b/drivers/scsi/osd/osd_uld.c +@@ -69,10 +69,10 @@ + #ifndef SCSI_OSD_MAJOR + # define SCSI_OSD_MAJOR 260 + #endif +-#define SCSI_OSD_MAX_MINOR 64 ++#define SCSI_OSD_MAX_MINOR MINORMASK + + static const char osd_name[] = "osd"; +-static const char *osd_version_string = "open-osd 0.2.0"; ++static const char *osd_version_string = "open-osd 0.2.1"; + + MODULE_AUTHOR("Boaz Harrosh <bharrosh@panasas.com>"); + MODULE_DESCRIPTION("open-osd Upper-Layer-Driver osd.ko"); +diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c +index 6a80749..027b6d0 100644 +--- a/drivers/spi/spi-topcliff-pch.c ++++ b/drivers/spi/spi-topcliff-pch.c +@@ -1717,7 +1717,7 @@ static int pch_spi_resume(struct pci_dev *pdev) + + #endif + +-static struct pci_driver pch_spi_pcidev = { ++static struct pci_driver pch_spi_pcidev_driver = { + .name = "pch_spi", + .id_table = pch_spi_pcidev_id, + .probe = pch_spi_probe, +@@ -1733,7 +1733,7 @@ static int __init pch_spi_init(void) + if (ret) + return ret; + +- ret = pci_register_driver(&pch_spi_pcidev); ++ ret = pci_register_driver(&pch_spi_pcidev_driver); + if (ret) + return ret; + +@@ -1743,7 +1743,7 @@ module_init(pch_spi_init); + + static void __exit pch_spi_exit(void) + { +- pci_unregister_driver(&pch_spi_pcidev); ++ pci_unregister_driver(&pch_spi_pcidev_driver); + platform_driver_unregister(&pch_spi_pd_driver); + } + module_exit(pch_spi_exit); +diff --git a/drivers/staging/media/lirc/lirc_serial.c b/drivers/staging/media/lirc/lirc_serial.c +index 8a060a8..1501e4e 100644 +--- a/drivers/staging/media/lirc/lirc_serial.c ++++ b/drivers/staging/media/lirc/lirc_serial.c +@@ -836,25 +836,22 @@ static int hardware_init_port(void) + return 0; + } + +-static int init_port(void) ++static int __devinit lirc_serial_probe(struct platform_device *dev) + { + int i, nlow, nhigh, result; + + result = request_irq(irq, irq_handler, + (share_irq ? IRQF_SHARED : 0), + LIRC_DRIVER_NAME, (void *)&hardware); +- +- switch (result) { +- case -EBUSY: +- printk(KERN_ERR LIRC_DRIVER_NAME ": IRQ %d busy\n", irq); +- return -EBUSY; +- case -EINVAL: +- printk(KERN_ERR LIRC_DRIVER_NAME +- ": Bad irq number or handler\n"); +- return -EINVAL; +- default: +- break; +- }; ++ if (result < 0) { ++ if (result == -EBUSY) ++ printk(KERN_ERR LIRC_DRIVER_NAME ": IRQ %d busy\n", ++ irq); ++ else if (result == -EINVAL) ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": Bad irq number or handler\n"); ++ return result; ++ } + + /* Reserve io region. */ + /* +@@ -875,11 +872,14 @@ static int init_port(void) + ": or compile the serial port driver as module and\n"); + printk(KERN_WARNING LIRC_DRIVER_NAME + ": make sure this module is loaded first\n"); +- return -EBUSY; ++ result = -EBUSY; ++ goto exit_free_irq; + } + +- if (hardware_init_port() < 0) +- return -EINVAL; ++ if (hardware_init_port() < 0) { ++ result = -EINVAL; ++ goto exit_release_region; ++ } + + /* Initialize pulse/space widths */ + init_timing_params(duty_cycle, freq); +@@ -911,6 +911,28 @@ static int init_port(void) + + dprintk("Interrupt %d, port %04x obtained\n", irq, io); + return 0; ++ ++exit_release_region: ++ if (iommap != 0) ++ release_mem_region(iommap, 8 << ioshift); ++ else ++ release_region(io, 8); ++exit_free_irq: ++ free_irq(irq, (void *)&hardware); ++ ++ return result; ++} ++ ++static int __devexit lirc_serial_remove(struct platform_device *dev) ++{ ++ free_irq(irq, (void *)&hardware); ++ ++ if (iommap != 0) ++ release_mem_region(iommap, 8 << ioshift); ++ else ++ release_region(io, 8); ++ ++ return 0; + } + + static int set_use_inc(void *data) +@@ -1076,16 +1098,6 @@ static struct lirc_driver driver = { + + static struct platform_device *lirc_serial_dev; + +-static int __devinit lirc_serial_probe(struct platform_device *dev) +-{ +- return 0; +-} +- +-static int __devexit lirc_serial_remove(struct platform_device *dev) +-{ +- return 0; +-} +- + static int lirc_serial_suspend(struct platform_device *dev, + pm_message_t state) + { +@@ -1112,10 +1124,8 @@ static int lirc_serial_resume(struct platform_device *dev) + { + unsigned long flags; + +- if (hardware_init_port() < 0) { +- lirc_serial_exit(); ++ if (hardware_init_port() < 0) + return -EINVAL; +- } + + spin_lock_irqsave(&hardware[type].lock, flags); + /* Enable Interrupt */ +@@ -1188,10 +1198,6 @@ static int __init lirc_serial_init_module(void) + { + int result; + +- result = lirc_serial_init(); +- if (result) +- return result; +- + switch (type) { + case LIRC_HOMEBREW: + case LIRC_IRDEO: +@@ -1211,8 +1217,7 @@ static int __init lirc_serial_init_module(void) + break; + #endif + default: +- result = -EINVAL; +- goto exit_serial_exit; ++ return -EINVAL; + } + if (!softcarrier) { + switch (type) { +@@ -1228,37 +1233,26 @@ static int __init lirc_serial_init_module(void) + } + } + +- result = init_port(); +- if (result < 0) +- goto exit_serial_exit; ++ result = lirc_serial_init(); ++ if (result) ++ return result; ++ + driver.features = hardware[type].features; + driver.dev = &lirc_serial_dev->dev; + driver.minor = lirc_register_driver(&driver); + if (driver.minor < 0) { + printk(KERN_ERR LIRC_DRIVER_NAME + ": register_chrdev failed!\n"); +- result = -EIO; +- goto exit_release; ++ lirc_serial_exit(); ++ return -EIO; + } + return 0; +-exit_release: +- release_region(io, 8); +-exit_serial_exit: +- lirc_serial_exit(); +- return result; + } + + static void __exit lirc_serial_exit_module(void) + { +- lirc_serial_exit(); +- +- free_irq(irq, (void *)&hardware); +- +- if (iommap != 0) +- release_mem_region(iommap, 8 << ioshift); +- else +- release_region(io, 8); + lirc_unregister_driver(driver.minor); ++ lirc_serial_exit(); + dprintk("cleaned up module\n"); + } + +diff --git a/drivers/tty/Kconfig b/drivers/tty/Kconfig +index b3d1741..830cd62 100644 +--- a/drivers/tty/Kconfig ++++ b/drivers/tty/Kconfig +@@ -365,7 +365,7 @@ config PPC_EPAPR_HV_BYTECHAN + + config PPC_EARLY_DEBUG_EHV_BC + bool "Early console (udbg) support for ePAPR hypervisors" +- depends on PPC_EPAPR_HV_BYTECHAN ++ depends on PPC_EPAPR_HV_BYTECHAN=y + help + Select this option to enable early console (a.k.a. "udbg") support + via an ePAPR byte channel. You also need to choose the byte channel +diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c +index c56378c..7099c31 100644 +--- a/drivers/video/omap2/dss/hdmi.c ++++ b/drivers/video/omap2/dss/hdmi.c +@@ -490,6 +490,7 @@ bool omapdss_hdmi_detect(void) + + int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) + { ++ struct omap_dss_hdmi_data *priv = dssdev->data; + int r = 0; + + DSSDBG("ENTER hdmi_display_enable\n"); +@@ -502,6 +503,8 @@ int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) + goto err0; + } + ++ hdmi.ip_data.hpd_gpio = priv->hpd_gpio; ++ + r = omap_dss_start_device(dssdev); + if (r) { + DSSERR("failed to start device\n"); +diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h +index 2c3443d..ec337b5d 100644 +--- a/drivers/video/omap2/dss/ti_hdmi.h ++++ b/drivers/video/omap2/dss/ti_hdmi.h +@@ -121,6 +121,10 @@ struct hdmi_ip_data { + const struct ti_hdmi_ip_ops *ops; + struct hdmi_config cfg; + struct hdmi_pll_info pll_data; ++ ++ /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */ ++ int hpd_gpio; ++ bool phy_tx_enabled; + }; + int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data); + void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data); +diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +index e1a6ce5..aad48a1 100644 +--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c ++++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +@@ -28,6 +28,7 @@ + #include <linux/delay.h> + #include <linux/string.h> + #include <linux/seq_file.h> ++#include <linux/gpio.h> + + #include "ti_hdmi_4xxx_ip.h" + #include "dss.h" +@@ -223,6 +224,49 @@ void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data) + hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); + } + ++static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data) ++{ ++ unsigned long flags; ++ bool hpd; ++ int r; ++ /* this should be in ti_hdmi_4xxx_ip private data */ ++ static DEFINE_SPINLOCK(phy_tx_lock); ++ ++ spin_lock_irqsave(&phy_tx_lock, flags); ++ ++ hpd = gpio_get_value(ip_data->hpd_gpio); ++ ++ if (hpd == ip_data->phy_tx_enabled) { ++ spin_unlock_irqrestore(&phy_tx_lock, flags); ++ return 0; ++ } ++ ++ if (hpd) ++ r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON); ++ else ++ r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); ++ ++ if (r) { ++ DSSERR("Failed to %s PHY TX power\n", ++ hpd ? "enable" : "disable"); ++ goto err; ++ } ++ ++ ip_data->phy_tx_enabled = hpd; ++err: ++ spin_unlock_irqrestore(&phy_tx_lock, flags); ++ return r; ++} ++ ++static irqreturn_t hpd_irq_handler(int irq, void *data) ++{ ++ struct hdmi_ip_data *ip_data = data; ++ ++ hdmi_check_hpd_state(ip_data); ++ ++ return IRQ_HANDLED; ++} ++ + int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data) + { + u16 r = 0; +@@ -232,10 +276,6 @@ int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data) + if (r) + return r; + +- r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON); +- if (r) +- return r; +- + /* + * Read address 0 in order to get the SCP reset done completed + * Dummy access performed to make sure reset is done +@@ -257,12 +297,32 @@ int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data) + /* Write to phy address 3 to change the polarity control */ + REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); + ++ r = request_threaded_irq(gpio_to_irq(ip_data->hpd_gpio), ++ NULL, hpd_irq_handler, ++ IRQF_DISABLED | IRQF_TRIGGER_RISING | ++ IRQF_TRIGGER_FALLING, "hpd", ip_data); ++ if (r) { ++ DSSERR("HPD IRQ request failed\n"); ++ hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); ++ return r; ++ } ++ ++ r = hdmi_check_hpd_state(ip_data); ++ if (r) { ++ free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data); ++ hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); ++ return r; ++ } ++ + return 0; + } + + void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data) + { ++ free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data); ++ + hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); ++ ip_data->phy_tx_enabled = false; + } + + static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data) +@@ -419,14 +479,7 @@ int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, + + bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data) + { +- int r; +- +- void __iomem *base = hdmi_core_sys_base(ip_data); +- +- /* HPD */ +- r = REG_GET(base, HDMI_CORE_SYS_SYS_STAT, 1, 1); +- +- return r == 1; ++ return gpio_get_value(ip_data->hpd_gpio); + } + + static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, +diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c +index d5aaca9..8497727 100644 +--- a/drivers/video/via/hw.c ++++ b/drivers/video/via/hw.c +@@ -1810,7 +1810,11 @@ static void hw_init(void) + break; + } + ++ /* magic required on VX900 for correct modesetting on IGA1 */ ++ via_write_reg_mask(VIACR, 0x45, 0x00, 0x01); ++ + /* probably this should go to the scaling code one day */ ++ via_write_reg_mask(VIACR, 0xFD, 0, 0x80); /* VX900 hw scale on IGA2 */ + viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters)); + + /* Fill VPIT Parameters */ +diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c +index 8464ea1..3c166d3 100644 +--- a/drivers/watchdog/hpwdt.c ++++ b/drivers/watchdog/hpwdt.c +@@ -231,7 +231,7 @@ static int __devinit cru_detect(unsigned long map_entry, + + cmn_regs.u1.reax = CRU_BIOS_SIGNATURE_VALUE; + +- set_memory_x((unsigned long)bios32_entrypoint, (2 * PAGE_SIZE)); ++ set_memory_x((unsigned long)bios32_map, 2); + asminline_call(&cmn_regs, bios32_entrypoint); + + if (cmn_regs.u1.ral != 0) { +@@ -250,7 +250,8 @@ static int __devinit cru_detect(unsigned long map_entry, + cru_rom_addr = + ioremap(cru_physical_address, cru_length); + if (cru_rom_addr) { +- set_memory_x((unsigned long)cru_rom_addr, cru_length); ++ set_memory_x((unsigned long)cru_rom_addr & PAGE_MASK, ++ (cru_length + PAGE_SIZE - 1) >> PAGE_SHIFT); + retval = 0; + } + } +diff --git a/fs/aio.c b/fs/aio.c +index 969beb0..67e4b90 100644 +--- a/fs/aio.c ++++ b/fs/aio.c +@@ -490,6 +490,8 @@ static void kiocb_batch_free(struct kioctx *ctx, struct kiocb_batch *batch) + kmem_cache_free(kiocb_cachep, req); + ctx->reqs_active--; + } ++ if (unlikely(!ctx->reqs_active && ctx->dead)) ++ wake_up_all(&ctx->wait); + spin_unlock_irq(&ctx->ctx_lock); + } + +diff --git a/fs/autofs4/autofs_i.h b/fs/autofs4/autofs_i.h +index 326dc08..308a98b 100644 +--- a/fs/autofs4/autofs_i.h ++++ b/fs/autofs4/autofs_i.h +@@ -110,6 +110,7 @@ struct autofs_sb_info { + int sub_version; + int min_proto; + int max_proto; ++ int compat_daemon; + unsigned long exp_timeout; + unsigned int type; + int reghost_enabled; +diff --git a/fs/autofs4/dev-ioctl.c b/fs/autofs4/dev-ioctl.c +index 509fe1e..56bac70 100644 +--- a/fs/autofs4/dev-ioctl.c ++++ b/fs/autofs4/dev-ioctl.c +@@ -385,6 +385,7 @@ static int autofs_dev_ioctl_setpipefd(struct file *fp, + sbi->pipefd = pipefd; + sbi->pipe = pipe; + sbi->catatonic = 0; ++ sbi->compat_daemon = is_compat_task(); + } + out: + mutex_unlock(&sbi->wq_mutex); +diff --git a/fs/autofs4/inode.c b/fs/autofs4/inode.c +index 8179f1a..98a5695 100644 +--- a/fs/autofs4/inode.c ++++ b/fs/autofs4/inode.c +@@ -19,6 +19,7 @@ + #include <linux/parser.h> + #include <linux/bitops.h> + #include <linux/magic.h> ++#include <linux/compat.h> + #include "autofs_i.h" + #include <linux/module.h> + +@@ -224,6 +225,7 @@ int autofs4_fill_super(struct super_block *s, void *data, int silent) + set_autofs_type_indirect(&sbi->type); + sbi->min_proto = 0; + sbi->max_proto = 0; ++ sbi->compat_daemon = is_compat_task(); + mutex_init(&sbi->wq_mutex); + spin_lock_init(&sbi->fs_lock); + sbi->queues = NULL; +diff --git a/fs/autofs4/waitq.c b/fs/autofs4/waitq.c +index e1fbdee..6861f61 100644 +--- a/fs/autofs4/waitq.c ++++ b/fs/autofs4/waitq.c +@@ -90,7 +90,24 @@ static int autofs4_write(struct file *file, const void *addr, int bytes) + + return (bytes > 0); + } +- ++ ++/* ++ * The autofs_v5 packet was misdesigned. ++ * ++ * The packets are identical on x86-32 and x86-64, but have different ++ * alignment. Which means that 'sizeof()' will give different results. ++ * Fix it up for the case of running 32-bit user mode on a 64-bit kernel. ++ */ ++static noinline size_t autofs_v5_packet_size(struct autofs_sb_info *sbi) ++{ ++ size_t pktsz = sizeof(struct autofs_v5_packet); ++#if defined(CONFIG_X86_64) && defined(CONFIG_COMPAT) ++ if (sbi->compat_daemon > 0) ++ pktsz -= 4; ++#endif ++ return pktsz; ++} ++ + static void autofs4_notify_daemon(struct autofs_sb_info *sbi, + struct autofs_wait_queue *wq, + int type) +@@ -147,8 +164,7 @@ static void autofs4_notify_daemon(struct autofs_sb_info *sbi, + { + struct autofs_v5_packet *packet = &pkt.v5_pkt.v5_packet; + +- pktsz = sizeof(*packet); +- ++ pktsz = autofs_v5_packet_size(sbi); + packet->wait_queue_token = wq->wait_queue_token; + packet->len = wq->name.len; + memcpy(packet->name, wq->name.name, wq->name.len); +diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c +index 21ac5ee..6ff96c6 100644 +--- a/fs/binfmt_elf.c ++++ b/fs/binfmt_elf.c +@@ -1421,7 +1421,7 @@ static int fill_thread_core_info(struct elf_thread_core_info *t, + for (i = 1; i < view->n; ++i) { + const struct user_regset *regset = &view->regsets[i]; + do_thread_regset_writeback(t->task, regset); +- if (regset->core_note_type && ++ if (regset->core_note_type && regset->get && + (!regset->active || regset->active(t->task, regset))) { + int ret; + size_t size = regset->n * regset->size; +diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c +index e4c3334..bf68b4f 100644 +--- a/fs/cifs/dir.c ++++ b/fs/cifs/dir.c +@@ -584,10 +584,26 @@ cifs_lookup(struct inode *parent_dir_inode, struct dentry *direntry, + * If either that or op not supported returned, follow + * the normal lookup. + */ +- if ((rc == 0) || (rc == -ENOENT)) ++ switch (rc) { ++ case 0: ++ /* ++ * The server may allow us to open things like ++ * FIFOs, but the client isn't set up to deal ++ * with that. If it's not a regular file, just ++ * close it and proceed as if it were a normal ++ * lookup. ++ */ ++ if (newInode && !S_ISREG(newInode->i_mode)) { ++ CIFSSMBClose(xid, pTcon, fileHandle); ++ break; ++ } ++ case -ENOENT: + posix_open = true; +- else if ((rc == -EINVAL) || (rc != -EOPNOTSUPP)) ++ case -EOPNOTSUPP: ++ break; ++ default: + pTcon->broken_posix_open = true; ++ } + } + if (!posix_open) + rc = cifs_get_inode_info_unix(&newInode, full_path, +diff --git a/include/linux/compat.h b/include/linux/compat.h +index 66ed067..d42bd48 100644 +--- a/include/linux/compat.h ++++ b/include/linux/compat.h +@@ -561,5 +561,9 @@ asmlinkage ssize_t compat_sys_process_vm_writev(compat_pid_t pid, + unsigned long liovcnt, const struct compat_iovec __user *rvec, + unsigned long riovcnt, unsigned long flags); + ++#else ++ ++#define is_compat_task() (0) ++ + #endif /* CONFIG_COMPAT */ + #endif /* _LINUX_COMPAT_H */ +diff --git a/include/linux/regset.h b/include/linux/regset.h +index 8abee65..686f373 100644 +--- a/include/linux/regset.h ++++ b/include/linux/regset.h +@@ -335,8 +335,11 @@ static inline int copy_regset_to_user(struct task_struct *target, + { + const struct user_regset *regset = &view->regsets[setno]; + ++ if (!regset->get) ++ return -EOPNOTSUPP; ++ + if (!access_ok(VERIFY_WRITE, data, size)) +- return -EIO; ++ return -EFAULT; + + return regset->get(target, regset, offset, size, NULL, data); + } +@@ -358,8 +361,11 @@ static inline int copy_regset_from_user(struct task_struct *target, + { + const struct user_regset *regset = &view->regsets[setno]; + ++ if (!regset->set) ++ return -EOPNOTSUPP; ++ + if (!access_ok(VERIFY_READ, data, size)) +- return -EIO; ++ return -EFAULT; + + return regset->set(target, regset, offset, size, NULL, data); + } +diff --git a/include/video/omapdss.h b/include/video/omapdss.h +index 378c7ed..6582c45 100644 +--- a/include/video/omapdss.h ++++ b/include/video/omapdss.h +@@ -575,6 +575,11 @@ struct omap_dss_device { + int (*get_backlight)(struct omap_dss_device *dssdev); + }; + ++struct omap_dss_hdmi_data ++{ ++ int hpd_gpio; ++}; ++ + struct omap_dss_driver { + struct device_driver driver; + +diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c +index cf2d7ae..ae95cd2 100644 +--- a/kernel/irq/manage.c ++++ b/kernel/irq/manage.c +@@ -985,6 +985,11 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) + + /* add new interrupt at end of irq queue */ + do { ++ /* ++ * Or all existing action->thread_mask bits, ++ * so we can find the next zero bit for this ++ * new action. ++ */ + thread_mask |= old->thread_mask; + old_ptr = &old->next; + old = *old_ptr; +@@ -993,14 +998,41 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) + } + + /* +- * Setup the thread mask for this irqaction. Unlikely to have +- * 32 resp 64 irqs sharing one line, but who knows. ++ * Setup the thread mask for this irqaction for ONESHOT. For ++ * !ONESHOT irqs the thread mask is 0 so we can avoid a ++ * conditional in irq_wake_thread(). + */ +- if (new->flags & IRQF_ONESHOT && thread_mask == ~0UL) { +- ret = -EBUSY; +- goto out_mask; ++ if (new->flags & IRQF_ONESHOT) { ++ /* ++ * Unlikely to have 32 resp 64 irqs sharing one line, ++ * but who knows. ++ */ ++ if (thread_mask == ~0UL) { ++ ret = -EBUSY; ++ goto out_mask; ++ } ++ /* ++ * The thread_mask for the action is or'ed to ++ * desc->thread_active to indicate that the ++ * IRQF_ONESHOT thread handler has been woken, but not ++ * yet finished. The bit is cleared when a thread ++ * completes. When all threads of a shared interrupt ++ * line have completed desc->threads_active becomes ++ * zero and the interrupt line is unmasked. See ++ * handle.c:irq_wake_thread() for further information. ++ * ++ * If no thread is woken by primary (hard irq context) ++ * interrupt handlers, then desc->threads_active is ++ * also checked for zero to unmask the irq line in the ++ * affected hard irq flow handlers ++ * (handle_[fasteoi|level]_irq). ++ * ++ * The new action gets the first zero bit of ++ * thread_mask assigned. See the loop above which or's ++ * all existing action->thread_mask bits. ++ */ ++ new->thread_mask = 1 << ffz(thread_mask); + } +- new->thread_mask = 1 << ffz(thread_mask); + + if (!shared) { + init_waitqueue_head(&desc->wait_for_threads); +diff --git a/kernel/kprobes.c b/kernel/kprobes.c +index faa39d1..bc90b87 100644 +--- a/kernel/kprobes.c ++++ b/kernel/kprobes.c +@@ -1334,8 +1334,10 @@ int __kprobes register_kprobe(struct kprobe *p) + if (!kernel_text_address((unsigned long) p->addr) || + in_kprobes_functions((unsigned long) p->addr) || + ftrace_text_reserved(p->addr, p->addr) || +- jump_label_text_reserved(p->addr, p->addr)) +- goto fail_with_jump_label; ++ jump_label_text_reserved(p->addr, p->addr)) { ++ ret = -EINVAL; ++ goto cannot_probe; ++ } + + /* User can pass only KPROBE_FLAG_DISABLED to register_kprobe */ + p->flags &= KPROBE_FLAG_DISABLED; +@@ -1352,7 +1354,7 @@ int __kprobes register_kprobe(struct kprobe *p) + * its code to prohibit unexpected unloading. + */ + if (unlikely(!try_module_get(probed_mod))) +- goto fail_with_jump_label; ++ goto cannot_probe; + + /* + * If the module freed .init.text, we couldn't insert +@@ -1361,7 +1363,7 @@ int __kprobes register_kprobe(struct kprobe *p) + if (within_module_init((unsigned long)p->addr, probed_mod) && + probed_mod->state != MODULE_STATE_COMING) { + module_put(probed_mod); +- goto fail_with_jump_label; ++ goto cannot_probe; + } + /* ret will be updated by following code */ + } +@@ -1409,7 +1411,7 @@ out: + + return ret; + +-fail_with_jump_label: ++cannot_probe: + preempt_enable(); + jump_label_unlock(); + return ret; +diff --git a/mm/huge_memory.c b/mm/huge_memory.c +index 33141f5..8f005e9 100644 +--- a/mm/huge_memory.c ++++ b/mm/huge_memory.c +@@ -642,6 +642,7 @@ static int __do_huge_pmd_anonymous_page(struct mm_struct *mm, + set_pmd_at(mm, haddr, pmd, entry); + prepare_pmd_huge_pte(pgtable, mm); + add_mm_counter(mm, MM_ANONPAGES, HPAGE_PMD_NR); ++ mm->nr_ptes++; + spin_unlock(&mm->page_table_lock); + } + +@@ -760,6 +761,7 @@ int copy_huge_pmd(struct mm_struct *dst_mm, struct mm_struct *src_mm, + pmd = pmd_mkold(pmd_wrprotect(pmd)); + set_pmd_at(dst_mm, addr, dst_pmd, pmd); + prepare_pmd_huge_pte(pgtable, dst_mm); ++ dst_mm->nr_ptes++; + + ret = 0; + out_unlock: +@@ -858,7 +860,6 @@ static int do_huge_pmd_wp_page_fallback(struct mm_struct *mm, + } + kfree(pages); + +- mm->nr_ptes++; + smp_wmb(); /* make pte visible before pmd */ + pmd_populate(mm, pmd, pgtable); + page_remove_rmap(page); +@@ -1017,6 +1018,7 @@ int zap_huge_pmd(struct mmu_gather *tlb, struct vm_area_struct *vma, + VM_BUG_ON(page_mapcount(page) < 0); + add_mm_counter(tlb->mm, MM_ANONPAGES, -HPAGE_PMD_NR); + VM_BUG_ON(!PageHead(page)); ++ tlb->mm->nr_ptes--; + spin_unlock(&tlb->mm->page_table_lock); + tlb_remove_page(tlb, page); + pte_free(tlb->mm, pgtable); +@@ -1356,7 +1358,6 @@ static int __split_huge_page_map(struct page *page, + pte_unmap(pte); + } + +- mm->nr_ptes++; + smp_wmb(); /* make pte visible before pmd */ + /* + * Up to this point the pmd is present and huge and +@@ -1969,7 +1970,6 @@ static void collapse_huge_page(struct mm_struct *mm, + set_pmd_at(mm, address, pmd, _pmd); + update_mmu_cache(vma, address, _pmd); + prepare_pmd_huge_pte(pgtable, mm); +- mm->nr_ptes--; + spin_unlock(&mm->page_table_lock); + + #ifndef CONFIG_NUMA +diff --git a/mm/memcontrol.c b/mm/memcontrol.c +index f538e9b..de67e91 100644 +--- a/mm/memcontrol.c ++++ b/mm/memcontrol.c +@@ -4502,6 +4502,9 @@ static void mem_cgroup_usage_unregister_event(struct cgroup *cgrp, + */ + BUG_ON(!thresholds); + ++ if (!thresholds->primary) ++ goto unlock; ++ + usage = mem_cgroup_usage(memcg, type == _MEMSWAP); + + /* Check if a threshold crossed before removing */ +@@ -4550,7 +4553,7 @@ swap_buffers: + + /* To be sure that nobody uses thresholds */ + synchronize_rcu(); +- ++unlock: + mutex_unlock(&memcg->thresholds_lock); + } + +diff --git a/mm/nommu.c b/mm/nommu.c +index ee7e57e..f59e170 100644 +--- a/mm/nommu.c ++++ b/mm/nommu.c +@@ -779,8 +779,6 @@ static void delete_vma_from_mm(struct vm_area_struct *vma) + + if (vma->vm_next) + vma->vm_next->vm_prev = vma->vm_prev; +- +- vma->vm_mm = NULL; + } + + /* +diff --git a/net/mac80211/rate.c b/net/mac80211/rate.c +index 5a5a776..7d84b87 100644 +--- a/net/mac80211/rate.c ++++ b/net/mac80211/rate.c +@@ -344,7 +344,7 @@ void rate_control_get_rate(struct ieee80211_sub_if_data *sdata, + for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) { + info->control.rates[i].idx = -1; + info->control.rates[i].flags = 0; +- info->control.rates[i].count = 1; ++ info->control.rates[i].count = 0; + } + + if (sdata->local->hw.flags & IEEE80211_HW_HAS_RATE_CONTROL) +diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c +index 05c8768..f3be54e 100644 +--- a/sound/pci/hda/hda_codec.c ++++ b/sound/pci/hda/hda_codec.c +@@ -1795,7 +1795,11 @@ static void put_vol_mute(struct hda_codec *codec, struct hda_amp_info *info, + parm = ch ? AC_AMP_SET_RIGHT : AC_AMP_SET_LEFT; + parm |= direction == HDA_OUTPUT ? AC_AMP_SET_OUTPUT : AC_AMP_SET_INPUT; + parm |= index << AC_AMP_SET_INDEX_SHIFT; +- parm |= val; ++ if ((val & HDA_AMP_MUTE) && !(info->amp_caps & AC_AMPCAP_MUTE) && ++ (info->amp_caps & AC_AMPCAP_MIN_MUTE)) ++ ; /* set the zero value as a fake mute */ ++ else ++ parm |= val; + snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_AMP_GAIN_MUTE, parm); + info->vol[ch] = val; + } +@@ -2062,7 +2066,7 @@ int snd_hda_mixer_amp_tlv(struct snd_kcontrol *kcontrol, int op_flag, + val1 = -((caps & AC_AMPCAP_OFFSET) >> AC_AMPCAP_OFFSET_SHIFT); + val1 += ofs; + val1 = ((int)val1) * ((int)val2); +- if (min_mute) ++ if (min_mute || (caps & AC_AMPCAP_MIN_MUTE)) + val2 |= TLV_DB_SCALE_MUTE; + if (put_user(SNDRV_CTL_TLVT_DB_SCALE, _tlv)) + return -EFAULT; +diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h +index 5644711..71f6744 100644 +--- a/sound/pci/hda/hda_codec.h ++++ b/sound/pci/hda/hda_codec.h +@@ -298,6 +298,9 @@ enum { + #define AC_AMPCAP_MUTE (1<<31) /* mute capable */ + #define AC_AMPCAP_MUTE_SHIFT 31 + ++/* driver-specific amp-caps: using bits 24-30 */ ++#define AC_AMPCAP_MIN_MUTE (1 << 30) /* min-volume = mute */ ++ + /* Connection list */ + #define AC_CLIST_LENGTH (0x7f<<0) + #define AC_CLIST_LONG (1<<7) +diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c +index 08bad5b..ae94929 100644 +--- a/sound/pci/hda/patch_conexant.c ++++ b/sound/pci/hda/patch_conexant.c +@@ -4132,7 +4132,8 @@ static int cx_auto_add_volume_idx(struct hda_codec *codec, const char *basename, + err = snd_hda_ctl_add(codec, nid, kctl); + if (err < 0) + return err; +- if (!(query_amp_caps(codec, nid, hda_dir) & AC_AMPCAP_MUTE)) ++ if (!(query_amp_caps(codec, nid, hda_dir) & ++ (AC_AMPCAP_MUTE | AC_AMPCAP_MIN_MUTE))) + break; + } + return 0; +@@ -4425,6 +4426,22 @@ static const struct snd_pci_quirk cxt_fixups[] = { + {} + }; + ++/* add "fake" mute amp-caps to DACs on cx5051 so that mixer mute switches ++ * can be created (bko#42825) ++ */ ++static void add_cx5051_fake_mutes(struct hda_codec *codec) ++{ ++ static hda_nid_t out_nids[] = { ++ 0x10, 0x11, 0 ++ }; ++ hda_nid_t *p; ++ ++ for (p = out_nids; *p; p++) ++ snd_hda_override_amp_caps(codec, *p, HDA_OUTPUT, ++ AC_AMPCAP_MIN_MUTE | ++ query_amp_caps(codec, *p, HDA_OUTPUT)); ++} ++ + static int patch_conexant_auto(struct hda_codec *codec) + { + struct conexant_spec *spec; +@@ -4443,6 +4460,9 @@ static int patch_conexant_auto(struct hda_codec *codec) + case 0x14f15045: + spec->single_adc_amp = 1; + break; ++ case 0x14f15051: ++ add_cx5051_fake_mutes(codec); ++ break; + } + + apply_pin_fixup(codec, cxt_fixups, cxt_pincfg_tbl); +diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c +index c4c8d78..3d8fbf4 100644 +--- a/sound/pci/hda/patch_realtek.c ++++ b/sound/pci/hda/patch_realtek.c +@@ -3695,7 +3695,7 @@ static void alc_auto_init_input_src(struct hda_codec *codec) + else + nums = spec->num_adc_nids; + for (c = 0; c < nums; c++) +- alc_mux_select(codec, 0, spec->cur_mux[c], true); ++ alc_mux_select(codec, c, spec->cur_mux[c], true); + } + + /* add mic boosts if needed */ +diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c +index ccdac27..ed67698 100644 +--- a/sound/pci/hda/patch_sigmatel.c ++++ b/sound/pci/hda/patch_sigmatel.c +@@ -4719,7 +4719,7 @@ static void stac92xx_hp_detect(struct hda_codec *codec) + unsigned int val = AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN; + if (no_hp_sensing(spec, i)) + continue; +- if (presence) ++ if (1 /*presence*/) + stac92xx_set_pinctl(codec, cfg->hp_pins[i], val); + #if 0 /* FIXME */ + /* Resetting the pinctl like below may lead to (a sort of) regressions +diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c +index 4c05e2b..971eaf0 100644 +--- a/sound/soc/imx/imx-ssi.c ++++ b/sound/soc/imx/imx-ssi.c +@@ -112,7 +112,7 @@ static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) + break; + case SND_SOC_DAIFMT_DSP_A: + /* data on rising edge of bclk, frame high 1clk before data */ +- strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS; ++ strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0 | SSI_STCR_TEFS; + break; + } + +diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c +index f42e8b9..ea909c5 100644 +--- a/sound/soc/soc-dapm.c ++++ b/sound/soc/soc-dapm.c +@@ -2982,9 +2982,13 @@ static void soc_dapm_shutdown_codec(struct snd_soc_dapm_context *dapm) + * standby. + */ + if (powerdown) { +- snd_soc_dapm_set_bias_level(dapm, SND_SOC_BIAS_PREPARE); ++ if (dapm->bias_level == SND_SOC_BIAS_ON) ++ snd_soc_dapm_set_bias_level(dapm, ++ SND_SOC_BIAS_PREPARE); + dapm_seq_run(dapm, &down_list, 0, false); +- snd_soc_dapm_set_bias_level(dapm, SND_SOC_BIAS_STANDBY); ++ if (dapm->bias_level == SND_SOC_BIAS_PREPARE) ++ snd_soc_dapm_set_bias_level(dapm, ++ SND_SOC_BIAS_STANDBY); + } + } + +@@ -2997,7 +3001,9 @@ void snd_soc_dapm_shutdown(struct snd_soc_card *card) + + list_for_each_entry(codec, &card->codec_dev_list, list) { + soc_dapm_shutdown_codec(&codec->dapm); +- snd_soc_dapm_set_bias_level(&codec->dapm, SND_SOC_BIAS_OFF); ++ if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) ++ snd_soc_dapm_set_bias_level(&codec->dapm, ++ SND_SOC_BIAS_OFF); + } + } + |