blob: 14b347b44745883a631adb575e63e16e7f3af937 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
|
BDEPEND=dev-util/gperf app-alternatives/yacc app-alternatives/lex >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=install prepare
DEPEND=sys-libs/readline:= sys-libs/zlib
DESCRIPTION=A Verilog simulation and synthesis tool
EAPI=7
HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog
INHERIT=autotools
KEYWORDS=amd64 ~arm ~arm64 ~ppc ~ppc64 ~riscv ~x86
LICENSE=LGPL-2.1
RDEPEND=sys-libs/readline:= sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/steveicarus/iverilog/archive/v11_0.tar.gz -> iverilog-11.0.tar.gz
_eclasses_=gnuconfig a397adda6984a4c423e28ac274c1ba98 toolchain-funcs 0c713337f7872f1a002cecaaea9bef73 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 5f49a16f67f81bdf873e3d1f10b10001 autotools d12ccbad07b44642a75ac97a3334d8e0
_md5_=0534d8af091e58e6f998b5e34700e039
|
GitWeb
